? 2009 integrated device technology, inc. dsc-7216/- idt and the idt logo are trademarks of integrated device technology, inc. 1 february 5, 2009 universal octal t1/e1/j1 liu with inte- grated clock adapter idt82p5088 features ? eight channel t1/e1/j1 long haul/short haul line interfaces ? supports hps (hitless protectio n switching) for 1+1 protection without external relays ? receiver sensitivity exceeds - 36 db@772khz and -43 db@1024 khz ? programmable t1/e1/j1 switchab ility allowing one bill of ma- terial for any line condition ? 3.3 v and 1.8 v power supply with 5 v tolerant inputs ? meets or exceeds specifications in - ansi t1.102, t1.403 and t1.408 - itu i.431, g.703,g.736, g.775 and g.823 - etsi 300-166, 300-233 and tbr 12/13 - at&t pub 62411 ? per channel software selectable on: - wave-shaping templates for short haul and long haul lbo (line build out) - line terminating impedance (t1:100 ? , j1:110 ?, e1:75 ?/ 120 ?) - adjustment of arbitrary pulse shape - ja (jitter attenuator) position (receive path and transmit path) - single rail/dual rail system interfaces - b8zs/hdb3/ami line encoding/decoding - active edge of transmit clock (tclk) and receive clock (rclk) - active level of transmit data (tdata) and receive data (rdata) - receiver or transmitter power down - high impedance setting for line drivers - prbs (pseudo random bit sequence) generation and detection with 2 15 -1 prbs polynomials for e1 - qrss (quasi random sequence signals) generation and detection with 2 20 -1 qrss polynomials for t1/j1 - 16-bit bpv (bipolar pulse viol ation)/excess zero/prbs or qrss error counter - analog loopback, digital loopback, remote loopback and inband loopback ? per channel cable attenuation indication ? adaptive receive sensitivity ? non-intrusive monitoring per itu g.772 specification ? short circuit protection for line drivers ? los (loss of signal) & ais (ala rm indication signal) detection ? jtag interface ? supports serial control interface, motorola and intel non-multi- plexed interfaces ? package: available in 256-pin pbga green package options available description the idt82p5088 is an eight port line in tereface that can be configured per port to any combination of t1, e1 or j1 ports. in receive path, an adaptive equalizer is integrated to remove t he distortion introduced by the cable attenuation. the idt82p5088 also per forms clock/data recovery, ami/ b8zs/hdb3 line decoding and detects and reports the los conditions. in transmit path, there is an ami/b8z s/hdb3 encoder, waveform shaper, lbos and jitter attenuator for each c hannel. the jitter attenuators in trans- mit path and receive path both can be disabled. the idt82p5088 supports both single rail and dual rail system interfaces. to facilitate the network maintenance, a prbs/qrss generation/detection circuit is integrated in each channel, and different types of loopbacks can be set on a per channel basis. four different kinds of line terminating impedance, 75 ? , 100 ?, 110 ? and 120 ? are selectable on a per channel basis. the chip also provides driver short-circuit protecti on and supports jtag boundary scanning. the idt82p5088 can be used in sdh/sonet, lan, wan, routers, wireless base stations, iads, im as, imaps, gateways, frame relay access devices, csu/dsu equipment, etc.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional block diag ram 2 february 5, 2009 functional block diagram figure-1 block diagram analog loopback one of the eight identical channels trst tck tms tdi tdo jtag tap b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery digital loopback remote loopback g.772 monitor transmitter internal termination receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn prbs detector iblc detector prbs generator iblc generator taos clock generator refa_out refb_out osci osco clk_sel[2:0] clk_gen_1.544 clk_gen_2.048 control interface ds / rd /sclk cs int a[10:0] d[7:1] refr mpm spien thz r w / wr /sdi reset gpio[1:0] d[0]/sdo vdddio / vdddc / vddar / vddat / vddax / vddap / vddab gndd / gnda
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter tables of contents 3 february 5, 2009 1 idt82p5088 pin configurations ................. ................ ................. .............. .............. ............ 9 2 pin description ...... ................ ................. ................ .............. .............. .............. ............. ....... 10 3 functional description ............... ................ ................ ............... .............. .............. .......... 17 3.1 t1/e1/j1 mode selection ................ ................. ................ ................. .............. .......... 17 3.2 transmit path ............ ................ ................. ................ ................. ................ ............... 1 7 3.2.1 transmit path system interf ace.............. .............. .............. ............ ........ 17 3.2.2 encoder ........... ................ ................ .............. ............... .............. .............. .......... 17 3.2.3 pulse shaper ............ ................. ................ ................. .............. .............. .......... 17 3.2.3.1 preset pulse templates .... ................ ................. .............. .............. ......... 17 3.2.3.2 lbo (line build out) ...... ................. ................ ................. .............. ......... 18 3.2.3.3 user-programmable arbitrary waveform .. ............. .............. ............ ....... 18 3.2.4 transmit path line interfac e................ ............... .............. .............. .......... 22 3.2.5 transmit path power down .. ................. ............... .............. .............. .......... 22 3.2.6 transmit jitter attenuator .. ................ ............... .............. .............. .......... 22 3.3 receive path .............. ................ ................. ................ ................. ................ ............... 24 3.3.1 receive internal terminatio n.................. .............. .............. .............. ........ 24 3.3.2 line monitor ............ ................ ................. ................ ................. .............. .......... 25 3.3.3 adaptive equalizer.... ................ ................ ............... .............. .............. .......... 25 3.3.4 receive sensitivity ............. ................ ................. ................ ................. .......... 25 3.3.5 data slicer .............. ................ ................. ................ ................. .............. .......... 25 3.3.6 cdr (clock & data recovery)... ............... ................ ................. ................ ............. 25 3.3.7 decoder ........... ................ ................ .............. ............... .............. .............. .......... 25 3.3.8 receive path system interface ................ .............. .............. ............ ........ 25 3.3.9 receive path power down.... ................ ................. .............. .............. .......... 25 3.3.10 g.772 non-intrus ive monitoring ........... ............... .............. .............. .......... 26 3.3.11 receive jitter attenuator... ................ ................. .............. .............. .......... 26 3.3.12 los and ais detection........ ................ ................. ................ ................. .......... 27 3.3.12.1 los detection.............. ................ ................. .............. .............. ......... 27 3.3.12.2 ais detection ............... ................ ................. .............. .............. ......... 29 3.4 transmit and detect internal patterns ...... .............. .............. .............. ........ 30 3.4.1 transmit all ones ... ................. ................ ................. .............. .............. .......... 30 3.4.2 transmit all zeros.... ................ ................ ............... .............. .............. .......... 30 3.4.3 prbs/qrss generation and detection..... ............. .............. ............ ........ 30 3.5 loopback ............ ................ ................ .............. .............. ............... .............. .............. ... 31 3.5.1 analog loopback ....... ................ ................ ............... .............. .............. .......... 31 3.5.2 digital loopback ..... ................. ................ ................. .............. .............. .......... 31 3.5.3 remote loopback....... ................ ................ ............... .............. .............. .......... 31 tables of contents
tables of contents 4 february 5, 2009 idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter 3.5.4 inband loopback...... ................. ................ ................. .............. .............. .......... 33 3.5.4.1 transmit activate/deacti vate loopback code.... .............. .............. ......... 33 3.5.4.2 receive activate/deact ivate loopback code..... .............. .............. ......... 33 3.5.4.3 automatic remote loopback .............. ............... .............. .............. ......... 33 3.6 error detection/counting and insertion ........... ................ ................. .......... 34 3.6.1 definition of line coding error .......... ............... .............. .............. .......... 34 3.6.2 error detection and counti ng ................ .............. .............. ............ ........ 34 3.6.3 bipolar violation and prbs error insertion ......... ................ ............. 35 3.7 line driver failure monitoring ............... ................. ................ ................. .......... 35 3.8 clock generator and tclk ....... ................ ................. ................ ................. .......... 36 3.8.1 clock generator.... ................. ................ ................. .............. .............. .......... 36 3.8.2 transmit clock (tclk)........ ................ ................. ................ ................. .......... 36 3.9 microprocessor interfac e .............. .............. ............... .............. .............. .......... 37 3.9.1 spi mode .......... ................. ................ ................ ............... .............. .............. .......... 37 3.9.2 parallel microprocessor interfac e ............... ................. ................ ................. .......... 37 3.10 interrupt handling ... ................. ................ ................ ................. ................ ............. 38 3.11 general purpose i/o .... ................ ................ ................. ................ ................. .......... 39 3.12 reset operation ......... ................. ................ ................ ................. ................ ............. 39 3.13 power supply ............ ................ ................. ................ ................. ................ ............... 3 9 4 programming information ............. .............. .............. ............... .............. .............. .......... 40 4.1 register list and map .. ............... ................ ................. ................ ................. .......... 40 4.2 reserved registers ...... ................ ................. ................ ................. .............. .......... 40 4.3 register description .... ................ ................. ................ ................. .............. .......... 42 4.3.1 global registers.... ................. ................ ................. .............. .............. .......... 42 4.3.2 per channel control regist ers .............. .............. .............. ............ ........ 44 4.3.3 transmit path control regi sters................ ................ ................. .......... 44 4.3.4 receive path control regi sters ............. .............. .............. ............ ........ 47 4.3.5 network diagnost ics control registers ................ ................. .......... 49 4.3.6 transmit and receive te rmination register .......... ................ ............. 52 4.3.7 interrupt control registers .............. ............... .............. .............. .......... 52 4.3.8 line status registers ....... ................ ................. ................ ................. .......... 55 4.3.9 interrupt status registers . ................ ............... .............. .............. .......... 58 4.3.10 counter registers ... ................ ................ ............... .............. .............. .......... 59 5 ieee std 1149.1 jtag test access po rt ............... ................ ................. .............. .......... 60 5.1 jtag instructions and instru ction register .... ................ ................. .......... 61 5.2 jtag data register .... ................. ................ ................ ................. ................ ............. 61 5.2.1 device identification regi ster (idr) ............. ................ ................. .......... 61 5.2.2 bypass register (br) ................. ................ ............... .............. .............. .......... 61 5.2.3 boundary scan regi ster (bsr) ............. ............... .............. .............. .......... 61 5.2.4 test access port controller . ................. .............. .............. ............ ........ 62 6 test specifications ......... ................ ................ ................. ................ ................. ............... .. 64
tables of contents 5 february 5, 2009 idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter 6.1 absolute maximum ratings ................ ................ ................ ................. ................ ............. 64 6.2 recommended operating conditions .. ............... ................ ................. ................ ............. 64 6.3 d.c. characteristics .... ................. ................ ................ ................. ................ ................. ... 65 6.4 t1/j1 line receiver elec trical characteristics .... ............... ................. ................ ............. 66 6.5 e1 line receiver electrical char acteristics ............... ................. .............. .............. .......... 67 6.6 t1/j1 line transmitter el ectrical characteristics . ................. ................ ................. .......... 67 6.7 e1 line transmitter electrical c haracteristics ............. ............... .............. .............. .......... 68 6.8 transmitter and re ceiver timing char acteristics ............. .............. .............. ............ ........ 69 6.9 jitter tolerance ......... ................ ................. ................ ................. ................ ................ ...... 70 6.9.1 t1/j1 mode .............. ................. ................ ................ ................. ................ ............. 70 6.9.2 e1 mode................. ................ ................. ................ ................. ................ ............... 7 1 6.10 jitter transfer ... ................ ................ ................. .............. .............. .............. ............. ......... 73 6.10.1 t1/j1 mode .............. ................. ................ ................ ................. ................ ............. 73 6.10.2 e1 mode................. ................ ................. ................ ................. ................ ............... 74 7 microcontroller interface timi ng characteristics ............ ................ ............. 77 7.1 motorola non-multiplexed mode .... ................ .............. ............... .............. .............. .......... 77 7.1.1 read cycle specification ....... .............. .............. ............... .............. .............. .......... 77 7.1.2 write cycle specification ....... .............. .............. ............... .............. .............. .......... 77 7.2 intel non-multiplexed mode ................ ................ ................ ................. ................ ............. 78 7.2.1 read cycle specification ....... .............. .............. ............... .............. .............. .......... 78 7.2.2 write cycle specification ....... .............. .............. ............... .............. .............. .......... 79 7.3 spi mode ........... ................ ................. ................ .............. .............. .............. ............. ....... 80
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter list of tables 6 february 5, 2009 table-1 pin description ....... ................ ................. ................ ................. ................ ................ ..... 10 table-2 transmit waveform value for e1 75 w ............ ................. ................ ................. ......... 19 table-3 transmit waveform value for e1 120 w ............. ................ ................. .............. ......... 19 table-4 transmit waveform value for t1 0~133 ft........... ................ ................. .............. ......... 19 table-5 transmit waveform value for t1 133~266 ft.............. .............. .............. .............. ....... 19 table-6 transmit waveform value for t1 266~399 ft.............. .............. .............. .............. ....... 20 table-7 transmit waveform value for t1 399~533 ft.............. .............. .............. .............. ....... 20 table-8 transmit waveform value for t1 533~655 ft.............. .............. .............. .............. ....... 20 table-9 transmit waveform value for j1 0~655 ft .................. .............. .............. .............. ....... 20 table-10 transmit waveform value for ds 1 0 db lbo............... .............. .............. ............ ....... 21 table-11 transmit waveform value for ds 1 -7.5 db lbo .......... .............. .............. ............ ....... 21 table-12 transmit waveform value for ds1 -15.0 db lbo ........ .............. .............. ............ ....... 21 table-13 transmit waveform value for ds1 -22.5 db lbo ........ .............. .............. ............ ....... 21 table-14 impedance matching for transmit ter ............... ................ ................. ................ ............ 22 table-15 related bit / register in c hapter 3.2.6 ............ ................ ................. ................ ............ 23 table-16 impedance matching for receiver .............. .............. ............... .............. .............. ......... 24 table-17 criteria of speed adjust ment start.................. ................ ................. ................ ............ 27 table-18 related bit / register in c hapter 3.3.11 ................. ................. .............. .............. ......... 27 table-19 los declare and clear criteria for short haul mode .. .............. .............. .............. ....... 28 table-20 los declare and clear criteria for long haul mode..... .............. .............. ............ ....... 29 table-21 ais condition ......... ................ ................. ................ ................. ................ ............... ...... 30 table-22 criteria for setting/clearing the prbs_s bit ..... ................. ................ ................. ......... 30 table-23 exz definition ........ ................ ................. ................ ................. ................ ............... ...... 34 table-24 reference clock selection........ ................ ................ ............... .............. .............. ......... 3 6 table-25 parallel microprocessor interfac e................ .............. ............... .............. .............. ......... 37 table-26 interrupt event................. ................. .............. .............. .............. .............. .............. ....... 38 table-27 global register list and map............... ................. ................ ................. .............. ......... 40 table-28 per channel register list and map ............ .............. ............... .............. .............. ......... 41 table-29 id: chip revision regi ster ................... ................. ................ .............. .............. ............ 42 table-30 rst: reset register ... ................ ................ ................. ................ ................. ............... . 42 table-31 mon: g.772 monitor control register....... ................ ............... .............. .............. ......... 42 table-32 gpio: general purpos e io pin definition regist er.................. .............. .............. ......... 42 table-33 refout: reference clock outp ut select register.... ............... .............. .............. ......... 43 table-34 intch: interrupt channel indi cation register........... ............... .............. .............. ......... 43 table-35 timer inte: timer in terrupt enable register...... ................ ................. .............. ......... 43 table-36 timer ints: timer in terrupt status register.... ................. ................ ................. ......... 44 list of tables
list of tables 7 february 5, 2009 idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter table-37 tie1 mode: t1 or e1 mode select regist er...................... ................ ................. ......... 44 table-38 tjacf: jitter attenuator configuration register for transmit path .............. ................ 44 table-39 tcf0: transmitter configurat ion register 0 fo r transmit path........... ................. ......... 44 table-40 tcf1: transmitter configurat ion register 1 fo r transmit path........... ................. ......... 45 table-41 tcf2: transmitter configurat ion register 2 fo r transmit path........... ................. ......... 46 table-42 tcf3: transmitter configurat ion register 3 fo r transmit path........... ................. ......... 46 table-43 tcf4: transmitter configurat ion register 4 fo r transmit path........... ................. ......... 46 table-44 rjacf: jitter attenuator c onfiguration register for receive pa th................. .............. 47 table-45 rcf0: receiver configurati on register 0 for receive path ...... .............. .............. ....... 47 table-46 rcf1: receiver configurati on register 1 for receive path ...... .............. .............. ....... 48 table-47 rcf2: receiver configurati on register 2 for receive path ...... .............. .............. ....... 49 table-48 maint0: maintenance function control register 0..... .............. .............. .............. ....... 49 table-49 maint1: maintenance function control register 1..... .............. .............. .............. ....... 49 table-50 maint2: maintenance function control register 2..... .............. .............. .............. ....... 50 table-51 maint3: maintenance function control register 3..... .............. .............. .............. ....... 50 table-52 maint4: maintenance function control register 4..... .............. .............. .............. ....... 51 table-53 maint5: maintenance function control register 5..... .............. .............. .............. ....... 51 table-54 maint6: maintenance function control register 6..... .............. .............. .............. ....... 51 table-55 term: transmit and receive termination configuration regist er ................ .............. 52 table-56 intenc0: interrupt mask register 0 ........ ................ ............... .............. .............. ......... 52 table-57 intenc1: interrupt mask register 1 ........ ................ ............... .............. .............. ......... 53 table-58 intes: interrupt tr igger edges select register ................. ................ ................. ......... 54 table-59 stat0: line status register 0 (real time status m onitor)............ .............. ............ ....... 55 table-60 stat1: line status register 1 (real time status m onitor)............ .............. ............ ....... 57 table-61 tjitt: jitter measure val ue indicate register (t ransmit path) ... .............. ............ ....... 57 table-62 tjitt: jitter measure value indicate register (rec eive path) .............. .............. ......... 57 table-63 ints0: interrupt stat us register 0 ....... ................. ................ ................. .............. ......... 58 table-64 ints1: interrupt stat us register 1 ....... ................. ................ ................. .............. ......... 59 table-65 cntl: error count er l-byte register 0....... .............. ............... .............. .............. ......... 59 table-66 cnth: error counter h-byte r egister 1 ............ ................. ................ ................. ......... 59 table-67 refc: e1 reference clock output control ....... ................. ................ ................. ......... 59 table-68 instruction regi ster description ......... ................ ................. ................ ................. ......... 61 table-69 device identification register description........ ................ ................. ................ ............ 61 table-70 tap controller state descripti on ................ .............. ............... .............. .............. ......... 62 table-71 jtag timing char acteristics ............... ................. ................ ................. .............. ......... 75
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter list of figures 8 february 5, 2009 figure-1 block diagram ....... ................ ................. ................ ................. ................ ................ ........ 2 figure-2 idt82p5088 pbga256 package pin assignment (t op view) ................. .............. .......... 9 figure-3 e1 waveform template diagram ............... .............. ............... .............. .............. .......... 17 figure-4 e1 pulse template test circuit .............. ................ ................. .............. .............. .......... 17 figure-5 dsx-1 waveform template ..... ................ ................ ............... .............. .............. .......... 18 figure-6 t1 pulse template te st circuit ........... ................. ................ ................. .............. .......... 18 figure-7 jitter attenuator ... ................ ................ ................. ................ ................. ................ ........ 22 figure-8 receive path function block dia gram .............. ................. ................ ................. .......... 24 figure-9 transmit/receive line circuit .. ................ ................ ............... .............. .............. .......... 24 figure-10 monitoring receive li ne in another chip ........ ................ ................. ................ ............. 25 figure-11 monitor transmit line in another chip ... ................ ................. .............. .............. .......... 25 figure-12 g.772 monitoring diagram ....... ................ .............. .............. .............. .............. ............. 2 6 figure-13 los declare and clear ......... ................. .............. .............. .............. .............. .............. .27 figure-14 analog loopback ......... ................ ................. ................ ................. .............. ............. .... 31 figure-15 digital loopback .... ................ ................. ................ ................. ................ ............... ....... 31 figure-16 remote loopback ...... ................ ................ ................. ................ ................. .............. ... 32 figure-17 auto report mode ............... ................ .............. .............. ............... .............. ............. .... 34 figure-18 manual report mode ................ .............. .............. .............. .............. .............. ............. .. 35 figure-19 clock generator .... ................ ................. ................ ................. ................ ................ ...... 36 figure-20 tclk operation flowchart .... ................. ................ .............. .............. .............. ............. 3 6 figure-21 read operation in spi mode ................. ................ ................. .............. .............. .......... 37 figure-22 write operation in spi mode ............ ................ ................. ................ ................. .......... 37 figure-23 jtag architecture .. ............... .............. .............. .............. ............... .............. ............ ..... 60 figure-24 jtag state diagram .. ................ ................ ................. ................ ................. ............... .. 63 figure-25 transmit system interface ti ming .................. ................ ................. ................ ............. 70 figure-26 receive system interface timi ng .............. .............. ............... .............. .............. .......... 70 figure-27 t1/j1 jitter tolerance perf ormance requirement ... ............... .............. .............. .......... 71 figure-28 e1 jitter tolerance perform ance requirement ........ ............... .............. .............. .......... 72 figure-29 t1/j1 jitter transfer performance requirement (at&t62411 / gr-253-core / tr-tsy- 000009) 74 figure-30 e1 jitter transfer perfor mance requirement (g.736) ................ .............. ............ ........ 75 figure-31 jtag interface timing ........ ................ ................. .............. .............. .............. ............. .. 76 figure-32 motorola non-multiplexed m ode read cycle ........... ............... .............. .............. .......... 77 figure-33 motorola non-multiplexed mode write cycle ........... ............... .............. .............. .......... 78 figure-34 intel non-multiple xed mode read cycle ......... ................ ................. ................ ............. 79 figure-35 intel non-multiplex ed mode write cycle ......... ................ ................. ................ ............. 79 figure-36 spi timing diagram ............ ................ .............. .............. ............... .............. .............. ... 80 list of figures
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter idt82p5088 pin configurat ions 9 february 5, 2009 1 idt82p5088 pin configurations figure-2 idt82p5088 pbga256 package pin assignment (top view) ttip4 tring4 vddat4 vddar4 vddar3 tring3 ttip3 ttip2 tring2 vddar1 tring1 ttip1 vddap reset refa_ out clk_ge n_1.544 tdn8 vddax4 gnda rtip4 vddat3 gnda vddax3 vddax2 vddat2 gnda gnda vddat1 osci refb_ out clk_sel 2 thz tdn7 td8/ tdp8 gnda rring4 gnda gnda gnda gnda vddar2 gnda rtip1 vddax1 osco clk_sel 1 gndd refr tdn6 td7/ tdp7 gnda gnda rring3 rtip3 gnda rtip2 rring2 gnda rring1 vddab gpio1 clk_ge n_2.048 clk_sel 0 gndd tdn4 td5/ tdp5 tdn5 td6/ tdp6 gndd gndd gndd gndd gndd gndd gndd gndd gpio0 vddax5 vddat5 ttip5 tdn2 td3/ tdp3 tdn3 td4/ tdp4 vdddio gndd gndd gndd gndd gndd gndd gndd gnda rtip5 gnda tring5 nc td1/ tdp1 tdn1 td2/ tdp2 vdddio gndd gndd gndd gndd gndd gndd gndd gnda rring5 gnda vddar5 nc tclk7 nc tclk8 vdddio vdddc vdddc vdddc gndd gndd gndd gndd rring6 vddat6 vddar6 tring6 tclk6 nc tclk5 nc vdddio vdddc vdddc vdddc vdddc vdddc vdddc vdddio rtip6 gnda vddax6 ttip6 tclk4 nc tclk3 nc vdddio vdddc vdddc vdddc vdddc vdddc vdddc vdddio gnda gnda vddax7 ttip7 tclk2 nc tclk1 cv8/ rdn8 rd8/ rdp8 vdddc vdddc vdddc vdddc vdddc vdddc vdddio rtip7 gnda gnda tring7 cv7/ rdn7 rd7/ rdp7 cv6/ rdn6 rd6/ rdp6 los5 rclk3 a0 a5 d4 d0/sdo mpm vdddio rring7 gnda vddar7 vddat7 cv5/ rdn5 rd5/ rdp5 cv4/ rdn4 los7 rclk5 los2 a1 a6 d5 ds / rd /sclk spien gndd gnda rtip8 rring8 vddar8 rd4/ rdp4 cv3/ rdn3 rd1/ rdp1 rclk7 los4 rclk2 a2 a7 a10 d3 r w / wr /sdi gndd gnda gnda gnda vddat8 rd3/ rdp3 rd2/ rdp2 los8 los6 rclk4 los1 a3 a8 d7 d2 cs vdddio trst tdo vddax8 tring8 cv2/ rdn2 cv1/ rdn1 rclk8 rclk6 los3 rclk1 a4 a9 d6 d1 int gndd tdi tms tck ttip8 1 2 3 4 5 6 7 8 9 10 11 1 2 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter pin description 10 february 5, 2009 notes: 1. the footprint ?n? (n = 1~8) represents one of the eight channels. 2. the name and address of the registers that contain the preceding bit. only the address of channel 1 register is listed, the r est addresses are represented by ?...?. users can find these omitted addresses in the register description section. 2 pin description table-1 pin description name type pin no. description pbga256 transmit and receive line interface ttip1 ttip2 ttip3 ttip4 ttip5 ttip6 ttip7 ttip8 tring1 tring2 tring3 tring4 tring5 tring6 tring7 tring8 output analog a12 a8 a7 a1 e16 j16 k16 t16 a11 a9 a6 a2 f16 h16 l16 r16 ttipn 1 /tringn: transmit bipolar tip/ring for channel 1~8 these pins are the differential line driver outputs and can be set to high impedance state globally or individually. a logic high on thz pin turns all these pins into high impedance state. when thz bit ( tcf1, 23h... ) 2 is set to ?1?, the ttipn/ tringn in the corresponding channel is set to high impedance state. in summary, these pins will become high impedance in the following conditions: ? thz pin is high: all ttipn/tringn enter high impedance; ? thzn bit is set to 1: the corresponding ttipn/tringn become high impedance; ? loss of mclk: all ttipn/tringn pins become high impedance; ? loss of tclkn: the corresponding ttipn/tringn become hz (exceptions: remote loopback; transmit inter- nal pattern by mclk); ? transmitter path power down: the corresponding ttipn/tringn become high impedance; ? after software reset; pin reset and power on: all ttipn/tringn enter high impedance. rtip1 rtip2 rtip3 rtip4 rtip5 rtip6 rtip7 rtip8 rring1 rring2 rring3 rring4 rring5 rring6 rring7 rring8 input analog c11 d8 d6 b4 f14 j13 l13 n14 d11 d9 d5 c4 g14 h13 m13 n15 rtipn/rringn: receive bipolar tip/ring for channel 1~8 these pins are the differential line receiver inputs.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter pin description 11 february 5, 2009 transmit and receive digital data interface td1/tdp1 td2/tdp2 td3/tdp3 td4/tdp4 td5/tdp5 td6/tdp6 td7/tdp7 td8/tdp8 tdn1 tdn2 tdn3 tdn4 tdn5 tdn6 tdn7 tdn8 input g2 g4 f2 f4 e2 e4 d2 c2 g3 f1 f3 e1 e3 d1 c1 b1 tdn: transmit data for channel 1~8 in single rail mode, the nrz data to be transmitted is input on these pins. data on tdn is sampled into the device on the active edge of tclkn. the active edge of tclkn is selected by the tclk_sel bit ( tcf0, 22h... ). data is encoded by ami, hdb3 or b8zs line code rules before being transmitted to the line. in this mode, tdnn should be connected to ground. tdpn/tdnn: positive/negative transmit data for channel 1~8 in dual rail mode, the nrz data to be transmitted is input on these pins. data on tdpn/tdnn is sampled into the device on the active edge of tclkn. the active edge of the tclkn is selected by the tclk_sel bit ( tcf0, 22h... ) the line code in dual rail mode is as follows: tclk1 tclk2 tclk3 tclk4 tclk5 tclk6 tclk7 tclk8 input l3 l1 k3 k1 j3 j1 h2 h4 tclkn: transmit clock for channel 1~8 these pins input 1.544 mhz for t1/j1 mode or 2.048 mhz for e1 mode transmit clock. the transmit data on tdn ort- dpn/tdnn is sampled into the device on the active edge of tclkn. if tclkn is missing 1 and the tclkn missing inter- rupt is not masked, an interrupt will be generated. rd1/rdp1 rd2/rdp2 rd3/rdp3 rd4/rdp4 rd5/rdp5 rd6/rdp6 rd7/rdp7 rd8/rdp8 cv1/rdn1 cv2/rdn2 cv3/rdn3 cv4/rdn4 cv5/rdn5 cv6/rdn6 cv7/rdn7 cv8/rdn8 output p3 r2 r1 p1 n2 m4 m2 l5 t2 t1 p2 n3 n1 m3 m1 l4 rdn: receive data for channel 1~8 in single rail mode, the nrz receive data is output on these pins. data is decoded according to ami, hdb3 or b8zs line code rules. the active level on rdn pin is selected by the rd_inv bit ( rcf0, 28h... ). cvn: code violation for channel 1~8 in single rail mode, the bpv/cv errors in received data streams will be reported by driving pi n cvn to high level for a full clock cycle. the b8zs/hdb3 line code violation can be indicated when the b8zs/hdb3 decoder is enabled. when ami decoder is selected, the bipolar violation can be indicated. rdpn/rdnn: positive/negative receive data for channel 1~8 in dual rail mode with clock & data recovery (cdr), these pins output the nrz data with the recovered clock. an active level on rdpn indicates the receipt of a positive pulse on rtipn/rringn while an active level on rdnn indi- cates the receipt of a negative pulse on rtipn/rringn. the active level on rdpn/rdnn is selected by the rd_inv bit ( rcf0, 28h... ). when cdr is disabled, these pins directly output the raw rz sliced data. the output data on rdn and rdpn/rdnn is updated on the active edge of rclkn. rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7 rclk8 output t6 p6 m6 r5 n5 t4 p4 t3 rclkn: receive clock for channel 1~8 these pins output 1.544 mhz for t1/j1 mode or 2.048 mhz for e1 mode receive clock. under los conditions, if raise bit ( maint1, 2ch... ) is ?1?, rclkn is derived from mclk. in clock recovery mode, these pins provide the clock recovered from the signal received on rtipn/rringn. the receive data (rdn in single rail mode or rdpn/rdnn in dual rail mode) is updated on the active edge of rclkn. the active edge is selected by the rclk_sel bit ( rcf0, 28h... ). if clock recovery is bypassed, rclkn is the exclusive or(xor) output of the dual rail sliced data rdpn and rdnn. this signal can be used in the applications with external clock recovery circuitry. table-1 pin description (continued) name type pin no. description pbga256 tdpn tdnn output pulse 0 0 space 0 1 positive pulse 1 0 negative pulse 1 1 space notes: 1. tclkn missing: the state of tclkn continues to be high level or low level over 70 clock cycles.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter pin description 12 february 5, 2009 los1 los2 los3 los4 los5 los6 los7 los8 output r6 n6 t5 p5 m5 r4 n4 r3 losn: loss of signal output for channel 1~8 these pins are used to indicate the loss of received signals. when losn pin becomes high, it indicates the loss of received signals in channel n. the losn pin will become low automatically when valid received signal is detected again. the criteria of loss of signal are described in 3.3.12 los and ais detection . clock generator osci input b13 osci: crystal oscillator input this pin is connected to an external clock source. the clock frequency of osci is defined by clk_sel[2:0]. the clock accuracy should be 32 ppm and duty cycle should be from 40% to 60%. osco output c13 osco: crystal oscillator output this pin outputs the inverted, buffered clock input from osci. clk_sel[0] clk_sel[1] clk_sel[2] input d15 c14 b15 clk_sel[2:0]: clock selection these three pins select the input clock signal: when the clk_sel[2] pin is low, the input clock signal is n x 1.544 mhz; when the clk_sel[2] pin is high, the input clock signal is n x 2.048 mhz. when the clk_sel[1:0] pins are ?00?, the n is 1; when the clk_sel[1:0] pins are ?01?, the n is 2; when the clk_sel[1:0] pins are ?10?, the n is 3; when the clk_sel[1:0] pins are ?11?, the n is 4. clk_sel[2:0] are schmitt-trigger inputs. clk_gen_1.54 4 output a16 clk_gen_1.544: clock generator 1.544 mhz output this pin outputs the 1.544 mhz clock signal generated by the clock generator. clk_gen_2.04 8 output d14 clk_gen_2.048: clock generator 2.048 mhz output this pin outputs the 2.048 mhz clock signal generated by the clock generator. refa_out output a15 refa_out: reference clock output a the frequecy is 2.048 mhz (e1) or 1.544 mhz (t1/j1) when no los is detected, this pin outputs a recovered clock from the clock and data recovery function block of one of the eight links. the link is selected by the ro1[2:0] bits ( refout, 07h ). when los is detected, this pin outputs mclk or high level, as selected by the refh_los bit ( refc, 3eh... ). note: mclk is a clock derived from osci using an internal pll, and the frequency is 2.048 mhz (e1) or 1.544 mhz (t1/j1). refb_out output b14 refb_out: reference clock output b the frequecy is 2.048 mhz (e1) or 1.544 mhz (t1/j1) when no los is detected, this pin outputs a recovered clock from the clock and data recovery function block of one of the eight links. the link is selected by the ro2[2:0] bits ( refout, 07h ). when los is detected, this pin outputs mclk or high level, as selected by the refh_los bit ( refc, 3eh... ). control interface reset input a14 reset : reset (active low) a low pulse for more than 100 ns on this pin resets the device. all the registers are accessible 2 ms after the reset. the reset pin is a schmitt-trigger input with a weak pull-up resistor. the osci clock must exist when the device is reset. gpio0 gpio1 output / input e13 d13 general purpose i/o [1:0] these two pins can be defined as input pins or output pins by the dir[1:0] bits ( gpio, 06h ) respectively. when the pins are input, their polarities are indicated by the level[1:0] bits ( gpio, 06h ) respectively. when the pins are out- put, their polarities are contro lled by the level[1:0] bits ( gpio, 06h ) respectively. gpio[1:0] are schmitt-trigger input/output with a pull-up resistor. table-1 pin description (continued) name type pin no. description pbga256
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter pin description 13 february 5, 2009 thz input b16 thz: transmit high-z a high level on this pin puts all the ttipn/tringn pins into high impedance state. thz is a schmitt-trigger input. int output t11 int : interrupt (active low) this is the open drain, active low interrupt output. this pin will stay low until all the active unmasked interrupt indica- tion bits are cleared. refr output c16 refr: this pin should be connected to ground via an external 10k resistor. cs input r11 cs : chip select (active low) this pin must be asserted low to enable the microprocessor interface. the signal must be asserted high at least once after power up to clear the internal test modes. a transition from high to low must occur on this pin for each read/ write operation and can not return to high until the operation is completed. cs is a schmitt-trigger input. a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 input m7 n7 p7 r7 t7 m8 n8 p8 r8 t8 p9 a[10:0]: address bus in parallel mode, the signals on these pins select the register for the microprocessor to access. in spi mode, these pins should be connected to ground. a[10:0] are schmitt-trigger inputs. d0 / sdo d1 d2 d3 d4 d5 d6 d7 output / input m10 t10 r10 p10 m9 n9 t9 r9 d[7:0]: bi-directional data bus in parallel mode, the signals on these pins are the data for read / write operation. in spi mode, the d[7:1] pins should be connected to the ground through a 10 k resistor. d[7:0] are schmitt-trigger inputs/outputs. sdo: serial data output in spi mode, the data is serially output on this pin. mpm input m11 mpm: micro controller mode in parallel mode, set this pin low for motorola mode or high for intel mode. in spi mode, set this pin to a fixed level (high or low). this pin is useless in spi mode. mpm is a schmitt-trigger input. r w / wr / sdi input p11 r w : read / write select in parallel motorola mode, this pin is active high for read operation and active low for write operation. wr : write strobe (active low) in parallel intel mode, this pin is active low for write operation. sdi: serial data input in spi mode, the address/control and/or data are serially input on this pin. r w / wr / sdi is a schmitt-trigger input. table-1 pin description (continued) name type pin no. description pbga256
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter pin description 14 february 5, 2009 ds / rd / sclk input n10 ds : data strobe (active low) in parallel motorola mode, this pin is active low. rd : read strobe (active low) in parallel intel mode, this pin is active low for read operation. sclk: serial clock in spi mode, this pin inputs the timing for the sdo and sdi pins. the signal on the sdo pin is updated on the falling edge of sclk, while the signal on the sdi pin is sampled on the rising edge of sclk. ds / rd / sclk is a schmitt-trigger input. spien input n11 spien: serial microprocessor interface enable when this pin is low, the microprocessor interface is in parallel mode. when this pin is high, the microprocessor interface is in spi mode. spien is a schmitt-trigger input. jtag signals trst input r13 trst : test reset (active low) a low signal on this pin resets the jtag test port. this pin is a schmitt-triggered input with an internal pull-up resistor. it must be connected to the reset pin or ground when jtag is not used. tms input t14 tms: test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. this pin is a schmitt-triggered input with an internal pull-up resistor. tck input t15 tck: test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is clocked out of the device on the falling edge of tck. this pin is a schmitt-triggered input with an internal pull-up resistor. tdi input t13 tdi: test input the test data is sampled at this pin on the rising edge of tck. this pin is a schmitt-triggered input with an internal pull-up resistor. tdo high-z r14 tdo: test output the test data are output on this pin. it is updated on the falling edge of tck. this pin is high-z except during the pro- cess of data scanning. power supplies and grounds vdddio power f5, g5, h5, j5, j12, k5, k12, l12, m12, r12 vdddio: 3.3 v i/o power supply vdddc power h6, h7, h8, j6, j7, j8, j9, j10, j11, k6, k7, k8, k9, k10, k11, l6, l7, l8, l9, l10, l11 vdddc: 1.8 v digital core power supply table-1 pin description (continued) name type pin no. description pbga256
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter pin description 15 february 5, 2009 vddar[1] vddar[2] vddar[3] vddar[4] vddar[5] vddar[6] vddar[7] vddar[8] power a10 c9 a5 a4 g16 h15 m15 n16 vddar[8:1]: 3.3 v power supply for receiver vddat[1] vddat[2] vddat[3] vddat[4] vddat[5] vddat[6] vddat[7] vddat[8] power b12 b9 b5 a3 e15 h14 m16 p16 vddat[8:1]: 3.3 v power supply for transmitter vddax[1] vddax[2] vddax[3] vddax[4] vddax[5] vddax[6] vddax[7] vddax[8] power c12 b8 b7 b2 e14 j15 k15 r15 vddax[8:1]: 3.3 v power supply for transmit driver vddap power a13 vddap: 3.3 v power analog pll vddab power d12 vddab: 3.3 v power analog bias gndd ground c15, d16, e5, e6, e7, e8, e9, e10, e11, e12, f6, f7, f8, f9, f10, f11, f12, g6, g7, g8, g9, g10, g11, g12, h9, h10, h11, h12, n12, p12, t12 gndd: digital ground table-1 pin description (continued) name type pin no. description pbga256
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter pin description 16 february 5, 2009 gnda ground b3, b6, b10, b11, c3, c5, c6, c7, c8, c10, d3, d4, d7, d10, f13, f15, g13, g15, j14, k13, k14, l14, l15, m14, n13, p13, p14, p15 gnda: analog ground others nc - g1, h1, h3, j2, j4, k2, k4, l2 nc: no connection no connection. these pins are not internally connected. table-1 pin description (continued) name type pin no. description pbga256
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 17 february 5, 2009 3 functional description 3.1 t1/e1/j1 mode selection the idt82p5088 can be used as an eight-channel e1 liu or an eight- channel t1/j1 liu. in e1 application, the temode bit ( t1e1 mode, 20h... ) should be set to ?0?. in t1/j1 application, the t1e1 bit should be set to ?1?. 3.2 transmit path the transmit path of each channel of the idt82p5088 consists of an encoder, an jitter attenuator, a waveform shaper, a set of lbos, a line driver and a programmable transmit termination. 3.2.1 transmit path system interface the transmit path system interface consists of tclkn pin, tdn/tdpn pin and tdnn pin. in e1 mode, the tc lkn is a 2.048 mhz clock. in t1/j1 mode, the tclkn is a 1.544 mhz clock. if the tclkn is missing for more than 70 mclk cycles, an interrupt wi ll be generated if it is not masked. transmit data is sampled on the tdn/ tdpn and tdnn pins by the active edge of tclkn. the active edge of tclkn can be selected by the tclk_sel bit ( tcf0, 22h... ). and the active level of the data on tdn/tdpn and tdnn can be selected by the td_inv bit ( tcf0, 22h... ). the transmit data from the system si de can be provided in two different ways: single rail and dual rail. in si ngle rail mode, only tdn pin is used for transmitting data and the t_md[1] bit ( tcf0, 22h... ) should be set to ?0?. in dual rail mode, both tdpn and tdnn pins are used for transmitting data, the t_md[1] bit ( tcf0, 22h... ) should be set to ?1?. 3.2.2 encoder when t1/j1 mode is selected, in si ngle rail mode, the encoder can be selected to be a b8zs encoder or an ami encoder by setting t_md[0] bit ( tcf0, 22h... ). when e1 mode is selected, in single rail mode, the encoder can be con- figured to be a hdb3 encoder or an ami encoder by setting t_md[0] bit ( tcf0, 22h... ). in both t1/j1 mode and e1 mode, when dual rail mode is selected (bit t_md[1] is ?1?), the encoder is by-pass ed. in the dual rail mode, a logic ?1? on the tdpn pin and a logic ?0? on the tdnn pin results in a negative pulse on the ttipn/tringn; a logic ?0? on td pn pin and a logic ?1? on tdnn pin results in a positive pulse on the ttipn/tringn. if both tdpn and tdnn are logic ?1? or logic ?0?, the ttip n/tringn outputs a space (refer to tdn, tdpn/tdnn pin description ). 3.2.3 pulse shaper the idt82p5088 provides three ways of manipulating the pulse shape before sending it. the first is to us e preset pulse templates for short haul application, the second is to use lb o (line build out) for long haul appli- cation and the other way is to use user-programmable arbitrary waveform template. 3.2.3.1 preset pulse templates for e1 applications, the pulse shape is shown in figure-3 according to the g.703 and the measuring diagram is shown in figure-4 . in internal impedance matching mode, if the cable impedance is 75 ? , the puls[3:0] bits ( tcf1, 23h... ) should be set to ?0000?; if the cable impedance is 120 ? , the puls[3:0] bits ( tcf1, 23h... ) should be set to ?0001?. in external impedance matching mode, for both e1/75 ? and e1/120 ? cable imped- ance, puls[3:0] should be set to ?0001?. figure-3 e1 waveform template diagram figure-4 e1 pulse template test circuit for t1 applications, the pulse shape is shown in figure-5 according to the t1.102 and the measuring diagram is shown in figure-6. this also meets the requirement of g.703, 2001. the cable length is divided into five grades, and there are five pulse templates used for each of the cable length. the pulse template is selected by puls[3:0] bits ( tcf1, 23h... ). -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 tim e in u nit intervals normalized amplitude idt82p5088 v out r load ttipn tringn note: 1. for r load = 75 ? (nom), v out (peak)=2.37v (nom) 2. for r load =120 ? (nom), v out (peak)=3.00v (nom)
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 18 february 5, 2009 figure-5 dsx-1 waveform template figure-6 t1 pulse template test circuit for j1 applications, the puls[3:0] ( tcf1, 23h.. .) should be set to ?0111?. table-14 lists these values. 3.2.3.2 lbo (line build out) to prevent the cross-talk at the fa r end, the output of ttip/tring could be attenuated before transmission for l ong haul applications. the fcc part 68 regulations specifies four grades of attenuation with a step of 7.5 db. three lbos are used to implement the pulse attenuation. the puls[3:0] bits ( tcf1, 23h... ) are used to select the attenuation grade. both table-14 and table-16 list these values. 3.2.3.3 user-programmable arbitrary waveform when the puls[3:0] bits are set to ?11xx?, user-progr ammable arbitrary waveform generator mode can be used in the corresponding channel. this allows the transmitter performance to be tuned for a wide variety of line con- dition or special application. each pulse shape can extend up to 4 uis (unit interval), addressed by ui[1:0] bits ( tcf3, 25h... ) and each ui is divided into 16 sub-phases, addressed by the samp[3:0] bits ( tcf3, 25h... ). the pulse amplitude of each phase is represented by a binary by te, within the range from +63 to - 63, stored in wdat[6:0] bits ( tcf4, 26h... ) in signed magnitude form. the most positive number +63 (d) repres ents the maximum positive amplitude of the transmit pulse while the most negative number -63 (d) represents the maximum negative amplitude of the transmit pulse. therefore, up to 64 bytes are used. for each channel, a 64 bytes ram is available. there are twelve standard templates which are stored in a local rom. user can select one of them as reference and make some changes to get the desired waveform. user can change the wave shape and the amplitude to get the desired pulse shape. in order to do this, firstl y, users can choose a set of waveform value from the following twelve tables , which is the most similar to the desired pulse shape. table-2 , table-3 , table-4 , table-5 , table-6 , table-7 , table-8 , table-9 , table-10 , table-11 , table-12 and table-13 list the sample data and scaling data of each of the twelve templates. then modify the cor- responding sample data to get the desired transmit pulse shape. secondly, through the value of sc al[5:0] bits increased or decreased by 1, the pulse amplitude can be scale d up or down at the percentage ratio against the standard pulse amplitude if needed. for different pulse shapes, the value of scal[5:0] bits and the scaling percentage ratio are different. the following twelve tables list these values. do the followings step by step, the desired waveform can be pro- grammed, based on the selected waveform template: (1).select the ui by ui[1:0] bits ( tcf3, 25h... ) (2).specify the sample address in the selected ui by samp [3:0] bits ( tcf3, 25h... ) (3).write sample data to wdat[6:0] bits ( tcf4, 26h... ). it contains the data to be stored in the ram, addressed by the selected ui and the corresponding sample address. (4).set the rw bit ( tcf3, 25h... ) to ?0? to implement writing data to ram, or to ?1? to implement read data from ram (5).implement the read from ram/write to ram by setting the done bit ( tcf3, 25h... ) repeat the above steps until all the sa mple data are written to or read from the internal ram. (6).write the scaling data to scal[5:0] bits ( tcf2, 24h... ) to scale the amplitude of the waveform based on the selected standard pulse amplitude when more than one ui is used to compose the pulse template, the over- lap of two consecutive pulses coul d make the pulse amplitude overflow (exceed the maximum limitation) if t he pulse amplitude is not set properly. this overflow is captured by dac_is bit ( ints1, 3bh... ), and, if enabled by the dac_ie bit ( intenc1, 34h... ), an interrupt will be generated. the following tables give all the sample data based on the preset pulse templates and lbos in detail for reference. for preset pulse templates and lbos, scaling up/down against the pul se amplitude is not supported. 1. table-2 transmit waveform value for e1 75 ? 2. table-3 transmit waveform value for e1 120 ? 3. table-4 transmit waveform value for t1 0~133 ft 4. table-5 transmit waveform value for t1 133~266 ft 5. table-6 transmit waveform value for t1 266~399 ft 6. table-7 transmit waveform value for t1 399~533 ft 7. table-8 transmit waveform value for t1 533~655 ft 8. table-9 transmit waveform value for j1 0~655 ft 9. table-10 transmit waveform value for ds1 0 db lbo 10. table-11 transmit waveform value for ds1 -7.5 db lbo 11. table-12 transmit waveform value for ds1 -15.0 db lbo -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 250 500 750 1000 1250 time (ns) normalized amplitude idt82p5088 ttipn tringn cable r load v out note: r load = 100 ? 5%
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 19 february 5, 2009 12. table-13 transmit waveform value for ds1 -22.5 db lbo table-2 transmit waveform value for e1 75 ? sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001100 0000000 0000000 0000000 5 0110000 0000000 0000000 0000000 6 0110000 0000000 0000000 0000000 7 0110000 0000000 0000000 0000000 8 0110000 0000000 0000000 0000000 9 0110000 0000000 0000000 0000000 10 0110000 0000000 0000000 0000000 11 0110000 0000000 0000000 0000000 12 0110000 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude. table-3 transmit waveform value for e1 120 ? sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001111 0000000 0000000 0000000 5 0111100 0000000 0000000 0000000 6 0111100 0000000 0000000 0000000 7 0111100 0000000 0000000 0000000 8 0111100 0000000 0000000 0000000 9 0111100 0000000 0000000 0000000 10 0111100 0000000 0000000 0000000 11 0111100 0000000 0000000 0000000 12 0111100 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude. table-4 transmit waveform value for t1 0~133 ft sample ui 1 ui 2 ui 3 ui 4 1 0010111 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 scal[5:0] = 110110 1 (default), one step change of this value of scal[5:0] results in 2% scaling up/down against the pulse amplitude. 1. in t1 mode, when arbitrary pulse for short haul application is configured, users should write ?110110? to scal[5:0] bits if no scaling is required. table-5 transmit waveform value for t1 133~266 ft sample ui 1 ui 2 ui 3 ui 4 1 0011011 1000011 0000000 0000000 2 0101110 1000010 0000000 0000000 3 0101100 1000001 0000000 0000000 4 0101010 0000000 0000000 0000000 5 0101001 0000000 0000000 0000000 6 0101000 0000000 0000000 0000000 7 0100111 0000000 0000000 0000000 8 0100110 0000000 0000000 0000000 9 0100101 0000000 0000000 0000000 10 1010000 0000000 0000000 0000000 11 1001111 0000000 0000000 0000000 12 1001101 0000000 0000000 0000000 13 1001010 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 20 february 5, 2009 table-6 transmit waveform value for t1 266~399 ft sample ui 1 ui 2 ui 3 ui 4 1 0011111 1000011 0000000 0000000 2 0110100 1000010 0000000 0000000 3 0101111 1000001 0000000 0000000 4 0101100 0000000 0000000 0000000 5 0101011 0000000 0000000 0000000 6 0101010 0000000 0000000 0000000 7 0101001 0000000 0000000 0000000 8 0101000 0000000 0000000 0000000 9 0100101 0000000 0000000 0000000 10 1010111 0000000 0000000 0000000 11 1010011 0000000 0000000 0000000 12 1010000 0000000 0000000 0000000 13 1001011 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4 table-7 transmit waveform value for t1 399~533 ft sample ui 1 ui 2 ui 3 ui 4 1 0100000 1000011 0000000 0000000 2 0111011 1000010 0000000 0000000 3 0110101 1000001 0000000 0000000 4 0101111 0000000 0000000 0000000 5 0101110 0000000 0000000 0000000 6 0101101 0000000 0000000 0000000 7 0101100 0000000 0000000 0000000 8 0101010 0000000 0000000 0000000 9 0101000 0000000 0000000 0000000 10 1011000 0000000 0000000 0000000 11 1011000 0000000 0000000 0000000 12 1010011 0000000 0000000 0000000 13 1001100 0000000 0000000 0000000 14 1001000 0000000 0000000 0000000 15 1000110 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4 table-8 transmit waveform value for t1 533~655 ft sample ui 1 ui 2 ui 3 ui 4 1 0100000 1000011 0000000 0000000 2 0111111 1000010 0000000 0000000 3 0111000 1000001 0000000 0000000 4 0110011 0000000 0000000 0000000 5 0101111 0000000 0000000 0000000 6 0101110 0000000 0000000 0000000 7 0101101 0000000 0000000 0000000 8 0101100 0000000 0000000 0000000 9 0101001 0000000 0000000 0000000 10 1011111 0000000 0000000 0000000 11 1011110 0000000 0000000 0000000 12 1010111 0000000 0000000 0000000 13 1001111 0000000 0000000 0000000 14 1001001 0000000 0000000 0000000 15 1000111 0000000 0000000 0000000 16 1000100 0000000 0000000 0000000 see table-4 table-9 transmit waveform value for j1 0~655 ft sample ui 1 ui 2 ui 3 ui 4 1 0010111 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 scal[5:0] = 110110 (default), one step change of this value of scal[5:0] results in 2% scaling up/down against the pulse amplitude.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 21 february 5, 2009 table-10 transmit waveform value for ds1 0 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0010111 1000010 0000000 0000000 2 0100111 1000001 0000000 0000000 3 0100111 0000000 0000000 0000000 4 0100110 0000000 0000000 0000000 5 0100101 0000000 0000000 0000000 6 0100101 0000000 0000000 0000000 7 0100101 0000000 0000000 0000000 8 0100100 0000000 0000000 0000000 9 0100011 0000000 0000000 0000000 10 1001010 0000000 0000000 0000000 11 1001010 0000000 0000000 0000000 12 1001001 0000000 0000000 0000000 13 1000111 0000000 0000000 0000000 14 1000101 0000000 0000000 0000000 15 1000100 0000000 0000000 0000000 16 1000011 0000000 0000000 0000000 scal[5:0] = 110110 (default), one step change of this value results in 2% scaling up/down against the pulse amplitude. table-11 transmit waveform value for ds1 -7.5 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0000000 0010100 0000010 0000000 2 0000010 0010010 0000010 0000000 3 0001001 0010000 0000010 0000000 4 0010011 0001110 0000010 0000000 5 0011101 0001100 0000010 0000000 6 0100101 0001011 0000001 0000000 7 0101011 0001010 0000001 0000000 8 0110001 0001001 0000001 0000000 9 0110110 0001000 0000001 0000000 10 0111010 0000111 0000001 0000000 11 0111001 0000110 0000001 0000000 12 0110000 0000101 0000001 0000000 13 0101000 0000100 0000000 0000000 14 0100000 0000100 0000000 0000000 15 0011010 0000011 0000000 0000000 16 0010111 0000011 0000000 0000000 scal[5:0] = 010001 (default), one step change of this value of scal[5:0] results in 6.25% scaling up/down against the pulse amplitude. table-12 transmit waveform value for ds1 -15.0 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0000000 0110101 0001111 0000011 2 0000000 0110011 0001101 0000010 3 0000000 0110000 0001100 0000010 4 0000001 0101101 0001011 0000010 5 0000100 0101010 0001010 0000010 6 0001000 0100111 0001001 0000001 7 0001110 0100100 0001000 0000001 8 0010100 0100001 0000111 0000001 9 0011011 0011110 0000110 0000001 10 0100010 0011100 0000110 0000001 11 0101010 0011010 0000101 0000001 12 0110000 0010111 0000101 0000001 13 0110101 0010101 0000100 0000001 14 0110111 0010100 0000100 0000000 15 0111000 0010010 0000011 0000000 16 0110111 0010000 0000011 0000000 scal[5:0] = 001000 (default), one step change of the value of scal[5:0] results in 12.5% scaling up/down against the pulse amplitude. table-13 transmit waveform value for ds1 -22.5 db lbo sample ui 1 ui 2 ui 3 ui 4 1 0000001 0110101 0011011 0000111 2 0000011 0110101 0011001 0000110 3 0000101 0110100 0010111 0000110 4 0001000 0110011 0010101 0000101 5 0001100 0110010 0010100 0000101 6 0010001 0110000 0010010 0000101 7 0010110 0101110 0010001 0000100 8 0011011 0101101 0010000 0000100 9 0100001 0101011 0001110 0000100 10 0100110 0101001 0001101 0000100 11 0101010 0100111 0001100 0000011 12 0101110 0100100 0001011 0000011 13 0110001 0100010 0001010 0000011 14 0110011 0100000 0001001 0000011 15 0110100 0011110 0001000 0000011 16 0110100 0011100 0001000 0000010 scal[5:0] = 000100 (default), one step change of this value of scal[5:0] results in 25% scaling up/down against the pulse amplitude.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 22 february 5, 2009 3.2.4 transmit path line interface the transmit line interface consists of ttipn pin and tringn pin. the impedance matching can be realized by the internal impedance matching circuit or the external impedance matc hing circuit. if t_term[2] is set to ?0?, the internal impedance matching circ uit will be selected. in this case, the t_term[1:0] bits ( term, 32h... ) can be set to choose 75 ? , 100 ? , 110 ? or 120 ? internal impedance of ttipn/tringn. if t_term[2] is set to ?1?, the internal impedance matching ci rcuit will be disabled. in this case, the external impedance matc hing circuit will be used to realize the imped- ance matching. for t1/j1 mode, the external impedance matching circuit for the transmitter is not supported. figure-9 shows the appropriate external components to connect with the cable for one channel. table-14 is the list of the recommended impedance matching for transmitter. the ttipn/tringn can be turned into high impedance globally by pull- ing thz pin to high or individua lly by setting the t_hz bit ( tcf1, 23h... ) to ?1?. in this state, the internal transmit circuits are still active. besides, in the following cases, tt ipn/tringn will also become high impedance: ? loss of mclk: all ttipn/tringn pins become high impedance; ? loss of tclkn: corresponding ttipn/tringn become hz (excep- tions: remote loopback; transmit internal pattern by mclk); ? transmit path power down; ? after software reset; pin reset and power on. note : the precision of the resistors should be better than 1% 3.2.5 transmit path power down the transmit path can be powered dow n individually by setting the t_off bit ( tcf0, 22h... ) to ?1?. in this case, the ttipn/tringn pins are turned into high impedance. 3.2.6 transmit jitter attenuator the transmit jitter attenuator of each link can be chosen to be used or not. this selection is made by the tja_e bit ( tjacf, 21h... ). the jitter attenuator consists of a fifo and a dpll, as shown in figure 7 . figure-7 jitter attenuator the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bits, as selected by the tja_dp[1:0] bits ( tjacf, 21h... ). accordingly, the constant delay produced by the jitter attenuator is 16 bits, 32 bits or 64 bits. the 128-bit fifo is used when large jitter tolerance is expe cted, and the 32-bit fifo is used in delay sensitive applications. the dpll is used to generate a de-jitte red clock to clock out the data stored in the fifo. the dpll can only attenuate the incoming jitter whose frequency is above corner frequency (cf). the jitter which frequency is lower than the cf passes through the dpll without any attenuation. in t1/j1 applications, the cf of the dpll can be 5 hz or 1.26 hz, as selected by the tja_bw bit ( tjacf, 21h... ). in e1 applica- tions, the cf of the dpll can be 6.77 hz or 0.87 hz, as selected by the tja_bw bit ( tjacf, 21h... ). the lower the cf is, the longer time is needed to achieve synchronization. if the incoming data moves faster than the outgoing data, the fifo will overflow. if the incoming data moves slower than the outgoing data, the fifo will underflow. the overflow or underflow is captured by the table-14 impedance matching for transmitter cable configuration internal termination external termination t_term[2:0] puls[3:0] r t t_term[2:0] puls[3:0] r t e1/75 ? 000 0000 0 ? 1xx 0001 9.4 ? e1/120 ? 001 0001 0001 t1/0~133 ft 010 0010 - - - t1/133~266 ft 0011 t1/266~399 ft 0100 t1/399~533 ft 0101 t1/533~655 ft 0110 j1/0~655 ft 011 0111 0 db lbo 010 1000 -7.5 db lbo 1001 -15.0 db lbo 1010 -22.5 db lbo 1011 fifo 32/64/128 dpll jittered data de-jittered data jittered clock de-jittered clock write pointer read pointer
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 23 february 5, 2009 tja_is bit. when the tja_is bit ( ints1, 3bh... ) is ?1?, an interrupt will be reported on the int pin if enabled by the tja_ie bit ( intenc1, 34h... ). to avoid overflowing or underflow ing, the ja-limit function can be enabled by setting the tja_limt bit ( tjacf, 21h... ). when the ja- limit function is enabled, the speed of the outgoing data will be adjusted automatically if the fifo is close to its full or emptiness. the criteria of speed adjustment start are listed in table 6. though the la-limit func- tion can reduce the possibility of fifo overflow and underflow, the quality of jitter attenuation is deteriorated. selected by the tjitt_test bit ( tjacf, 21h... ), the real time interval between the read and write poi nter of the fifo or the peak-peak interval between the read and write pointer of the fifo can be indicated in the tjitt[6:0] bits. when the tj itt_test bit is ?0?, the current interval between the read and write pointer of the fifo will be written into the tjitt[6:0] bits. when the tjitt_test bit is ?1?, the current interval is compared with the old one in the tjitt[6:0] bits and the larger one will be indicated by the tjitt[6:0] bits. the performance of receive jitter attenuator meets the itut i.431, g.703, g.736 - 739, g.823, g.824, etsi 300011, etsi tbr 12/13, at&t tr62411, tr43802, tr-tsy 009, tr-tsy 253, tr-try 499 standards. refer to chapter 7.10 jitter tolerance and chapter 7.10 jitter tolerance for details. table-15 related bit / re gister in chapter 3.2.6 bit register address (hex) tja_e transmit jitter attenuation configura- tion x21h tja_dp[1:0] tja_bw tja_limt tjitt_test tja_is interrupt status 1 x3bh tja_ie interrupt enable control 1 x34h tjitt[6:0] transmit jitter measure value indica- tion x38h
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 24 february 5, 2009 3.3 receive path the receive path consists of receiv e internal termination, monitor gain, amplitude/wave shape detector, digital tuning controller, adaptive equalizer, data slicer, cdr (clock and data recovery), jitter attenuator, decoder and los/ais detector. refer to figure-8 . 3.3.1 receive internal termination the impedance matching can be real ized by the internal impedance matching circuit or the external impedance matching circuit. if r_term[2] is set to ?0?, the internal impedance ma tching circuit will be selected. in this case, the r_term[1:0] bits ( term, 32h... ) can be set to choose 75 ? , 100 ? , 110 ? or 120 ? internal impedance of rtipn/rringn. if r_term[2] is set to ?1?, the internal impedance ma tching circuit will be disabled. in this case, the external impedance matching ci rcuit will be used to realize the impedance matching. figure-9 shows the appropriate exter nal components to connect with the cable for one channel. table-16 is the list of the recommended imped- ance matching for receiver. figure-8 receive path function block diagram figure-9 transmit/receive line circuit table-16 impedance matching for receiver cable configuration internal te rmination external termination r_term[2:0] r r r_term[2:0] r r e1/75 ? 000 120 ? 1xx 75 ? e1/120 ? 001 120 ? t1 010 100 ? j1 011 110 ? adaptive equalizer/ monitor gain los/ais detector data slicer decoder los rclk rdp rdn rtip clock and data recovery receive internal termination rring jitter attenuator a b ? ? ?? r x line r r ? ? t x line r t r t rtip rring tring ttip idt82p5088 (one of the eight identical links) vddax vddax d4 d3 d2 d1 1 : 1 2 : 1 d6 d5 d8 d7 cp vddar vddar note : 1. common decoupling capacitor 2. cp 0-560 (pf) 3. d1 - d8, motorola - mbr0540t1; international rectifier - 11dq04 or 10bq060 ? f gnda vddax 68 f 1 3.3 v ? f gnda vddar 68 f 3.3 v 1
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 25 february 5, 2009 3.3.2 line monitor in both t1/j1 and e1 short haul applic ations, the non-intrusive monitor- ing on channels located in other chips can be performed by tapping the mon- itored channel through a high impedanc e bridging circuit. refer to figure- 10 and figure-11 . after a high resistance bridging circui t, the signal arriving at the rtipn/ rringn is dramatically attenuated. to compensate this attenuation, the monitor gain can be used to boost the signal by 22 db, 26 db and 32 db, selected by mg[1:0] bits ( rcf2, 2ah... ). for normal operation, the monitor gain should be set to 0 db. figure-10 monitoring receive line in another chip figure-11 monitor transmit line in another chip 3.3.3 adaptive equalizer the adaptive equalizer can remove most of the signal distortion due to intersymbol interference caused by cable attenuation. it can be enabled or disabled by setting eq_on bit to ?1? or ?0? ( rcf1, 29h... ). the amplitude/wave shape detector keeps on measuring the ampli- tude/wave shape of the incoming signal s during an observation period. this observation period can be 32, 64, 128 or 256 symbol periods, as selected by updw[1:0] bits ( rcf2, 2ah... ). a shorter observation period allows quicker response to pulse amplitude variation while a longer observation period can minimize the possible overshoots. the default observation period is 128 symbol periods. based on the observed peak value for a period, the equalizer will be adjusted to achieve a normali zed signal. latt[4:0] bits ( stat1, 37h... ) indicate the signal attenuation introduc ed by the cable in approximately 2 db per step. 3.3.4 receive sensitivity for short haul application, the receive sensitivity for both e1 and t1/ j1 is -10 db. for long haul application, the receive sensitivity is -43 db for e1 and -36 db for t1/j1. 3.3.5 data slicer the data slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. the threshold can be 40%, 50%, 60% or 70%, as selected by the slice[1:0] bits ( rcf2, 2ah... ). the output of the data slicer is forwarded to the cdr (clock & data recovery) unit or to the rdpn/rdnn pi ns directly if the cdr is disabled. 3.3.6 cdr (clock & data recovery) the cdr is used to recover the clock from the received signals. the recovered clock tracks the jitter in th e data output from the data slicer and keeps the phase relationship betw een data and clock during the absence of the incoming pulse. the cdr can also be by-passed in the dual rail mode. when cdr is by-passed, the data from the data slicer is output to the rdpn/rdnn pins directly. 3.3.7 decoder in t1/j1 applications, the r_md[1:0] bits ( rcf0, 28h... ) is used to select the ami decoder or b8zs decoder. in e1 applications, the r_md[1:0] bits ( rcf0, 28h... ) are used to select the ami decoder or hdb3 decoder. 3.3.8 receive path system interface the receive path system interface consists of rclkn pin, rdn/rdpn pin and rdnn pin. in e1 mode, the rclkn outputs a recovered 2.048 mhz clock. in t1/j1 mode, the rclkn outputs a recovered 1.544 mhz clock. the received data is updated on the rdn/rdpn and rdnn pins on the active edge of rclkn. the active edge of rclkn can be selected by the rclk_sel bit ( rcf0, 28h... ). and the active level of the data on rdn/ rdpn and rdnn can also be se lected by the rd_inv bit ( rcf0, 28h... ). the received data can be output to the system side in two different ways: single rail or dual rail, as selected by r_md bit [1] ( rcf0,28h... ). in single rail mode, only rdn pin is used to output data and the rdnn/cvn pin is used to report the received errors. in dual rail mode, both rdpn pin and rdnn pin are used for outputting data. in the receive dual rail mode, t he cdr unit can be by-passed by setting r_md[1:0] to ?11? (binary). in this situation, the output data from the data slicer will be output to the rdpn/ rdnn pins directly, and the rclkn out- puts the exclusive or (xor) of the rdpn and rdnn. 3.3.9 receive path power down the receive path can be powered dow n individually by setting r_off bit ( rcf0, 28h... ) to ?1?. in this case, the rclkn, rdn/rdpn, rdpn and losn will be logic low. rtip rring rtip rring normal receive mode monitor mode dsx cross connect point r monitor gain =22/26/32db monitor gain=0db ttip tring rtip rring normal transmit mode monitor mode dsx cross connect point r monitor gain monitor gain =22/26/32db
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 26 february 5, 2009 3.3.10 g.772 non-intrusive monitoring in applications using only seven channels, channel 1 can be configured to monitor the data received or transmitted in any one of the remaining chan- nels. the mon[3:0] bits ( mon, 05h ) determine which channel and which direction (transmit/receive) will be m onitored. the monitoring is non-intru- sive per itu-t g.772. figure-12 illustrates the concept. the monitored line signal (transmi t or receive) goes through channel 1's clock and data recovery. the signal can be observed digitally at the rclk1, rd1/rdp1 and rdn1. if channel 1 is configured to remote loop- back while in the monitoring mode, the monitored data will be output on ttip1/tring1. figure-12 g.772 monitoring diagram 3.3.11 receive jitter attenuator the receive jitter attenuator of each link can be chosen to be used or not. this selection is made by the rja_e bit ( rjacf, 27h... ). the jitter attenuator consists of a fifo and a dpll, as shown in figure 7 . the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bi ts, as selected by the rja_dp[1:0] bits ( rjacf, 27h... ). accordingly, the constant delay produced by the jitter attenuator is 16 bits, 32 bits or 64 bits. the 128-bit fifo is used when large jitter tolerance is expected, while the 32-bit fifo is used in delay sensitive applications. the dpll is used to generate a de-jitte red clock to clock out the data stored in the fifo. the dpll can only attenuate the incoming jitter whose frequency is above corner frequency (cf). the jitter whose frequency is lower than the cf passes through the dpll without any attenuation. in t1/j1 applications, the cf of the dpll can be 5 hz or 1.26 hz, as selected by the rja_bw bit. in e1 applications, the cf of the dpll can be 6.77 hz or 0.87 hz, as selected by the rja_bw bit ( rjacf, 27h... ). the lower the cf is, the longer time is needed to achieve synchronization. if the incoming data moves faster than the outgoing data, the fifo will overflow. if the incoming data moves slower than the outgoing data, the fifo will underflow. the overflow or underflow is captured by the channel n (n > 2) b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery transmitter internal termination receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn channel 1 b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery transmitter internal termination receiver internal termination tclk1 tdn1 tdn/tdp1 rclk1 cvn/rdn1 los1 rdn/rdp1 rring1 ttip1 tring1 rtip1 remote loopback g.772 monitor
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 27 february 5, 2009 rja_is bit ( ints1, 3bh... ). when the rja_is bit is ?1?, an interrupt will be reported on the int pin if enabled by the rja_ie bit ( intenc1, 34h... ). to avoid overflow or underflow, the ja-limit function can be enabled by setting the rja_limt bit ( rjacf, 27h... ). when the ja-limit func- tion is enabled, the speed of the out going data will be adjusted automat- ically if the fifo is close to its fu ll or emptiness. the criteria of speed adjustment start are listed in table 17. though the ja-limit function can reduce the possibility of fifo overflow and underflow, the quality of jitter attenuation is deteriorated. selected by the rjitt_test bit ( rjacf, 27h... ), the real time interval between the read and write poi nter of the fifo or the peak-peak interval between the read and write pointer of the fifo can be indicated in the rjitt[6:0] bits ( rjitt, 39h... ). when the rjitt_test bit is ?0?, the current interval between the read and write pointer of the fifo will be written into the rjitt[6:0] bits. wh en the rjitt_test bit is ?1?, the current interval will be compared with the old one in the rjitt[6:0] bits and the larger one will be indicated by the rjitt[6:0] bits. the performance of receive jitter attenuator meets the itu-t i.431, g.703, g.736 - 739, g.823, g.824, etsi 300011, etsi tbr 12/13, at&t tr62411, tr43802, tr-tsy 009, tr-tsy 253, tr-try 499 standards. refer to chapter 7.10 jitter tolerance and chapter 7.11 jitter transfer for details. 3.3.12 los and ais detection 3.3.12.1los detection the loss of signal detector monitors the amplitude of the incoming sig- nal level and pulse density of the received signal on rtipn and rringn. ? los declare (los=1) a los is detected when the incoming signal has ?no transitions?, i.e., when the signal level is less than q db below nominal for n consecutive pulse intervals. here n is defined by lac bit ( maint1, 2ch... ). los will be declared by pulling losn pin to high (los=1) and los interrupt will be gen- erated if it is not masked. ? los clear (los=0) the los is cleared when the incoming signal has ?transitions?, i.e., when the signal level is greater t han p db below nominal and has an aver- age pulse density of at least 12.5% for m consecutive pulse intervals, start- ing with the receipt of a pulse. here m is defined by lac bit ( maint1, 2ch... ). los status is cleared by pulling losn pin to low. figure-13 los declare and clear ? los detect level threshold in short haul mode, the amplitude threshold q is fixed on 800 mvpp, while p=q+200 mvpp (200 mvpp is the los level detect hysteresis). in line monitor mode, the amplitude threshold q is fixed on 1600 mvpp, while p=q+400 mvpp (400 mvpp is the los level detect hysteresis). in long haul mode, the value of q can be selected by los[4:0] bit ( rcf1, 29h... ), while p=q+4 db (4 db is the los level detect hysteresis). the los[4:0] default value is 10101 (-46 db). ? criteria for declare and clear of a los detect the detection supports the ansi t1.231 and i.431 for t1/j1 mode and g.775 and etsi 300233/i.431 for e1 mode. the criteria can be selected by lac bit ( maint1, 2ch... ) and te_mode bit ( t1e1 mode, 20h... ). table-19 and table-20 summarize los declare and clear criteria for both short haul and long haul application. ? all ones output during los on the system side, the rdpn/rdnn wi ll reflect the input pulse ?transi- tion? at the rtipn/rringn side and out put recovery clock (but the quality of the output clock can not be guaranteed when the input level is lower than table-17 criteria of speed adjustment start fifo depth criteria of speed adjustment start 32 bits 2-bit close to full or empty 64 bits 3-bit close to full or empty 128 bits 4-bit close to full or empty table-18 related bit / register in chapter 3.3.11 bit register address (hex) rja_e receive jitter attenuation configura- tion x27h rja_dp[1:0] rja_bw rja_limt rjitt_test rja_is interrupt status 1 x3bh rja_ie interrupt enable control 1 x34h rjitt[6:0] receive jitter measure value indication x39h signal levelp density=ok los=1 los=0
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 28 february 5, 2009 the maximum receive sensitivity) when raise bit ( maint1, 2ch... ) is 0; or output all ones as ais when raise bit ( maint1, 2ch... ) is 1. in this case rclkn output is replaced by mclk. on the line side, the ttipn/tringn will output all ones as ais when atao bit ( maint1, 2ch... ) is 1. the all ones pattern uses mclk as the reference clock. los indicator is always active for all kinds of loopback modes. table-19 los declare and clear criteria for short haul mode control bit los declare threshold los clear threshold temode lac 1=t1/j1 0=t1.231 level < 800 mvpp n=175 bits level > 1 vpp m=128 bits 12.5% mark density <100 consecutive zeroes 1=i.431 level < 800 mvpp n=1544 bits level > 1 vpp m=128 bits 12.5% mark density <100 consecutive zeroes 0=e1 0=g.775 level < 800 mvpp n=32 bits level > 1 vpp m=32 bits 12.5% mark density <16 consecutive zeroes 1=i.431/etsi level < 800 mvpp n=2048 bits level > 1 vpp m=32 bits 12.5% mark density <16 consecutive zeroes
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 29 february 5, 2009 3.3.12.2ais detection the alarm indication signal can be detected by the idt82p5088 when the clock&data recovery unit is enabled. the status of ais detection is reflected in the ais_s bit ( stat0, 36h...) . in t1/j1 applications, the criteria for declaring/clearing ais detection are in compliance with the ansi t1.231. in e1 applications, the criter ia for declaring/clearing ais detection comply with the itu g.775 or the etsi 300233, as selected by the lac bit ( maint1,2ch... ). table-21 summarizes different criteria for ais detection declaring/clearing. table-20 los declare and clear criteria for long haul mode control bit los declare thres hold los clear threshold note temode lac los[4:0] q (db) 1=t1/j1 0 t1.231 00000 00001 ? 10001 ? 10101 10110-11111 -4 -6 ? -38 ? -46 -48 level < q n=175 bits level > q+ 4db m=128 bits 12.5% mark density <100 consecutive zeroes 1 - 00000 ? 00110 -4 -16 level < q n=1544 bits level > q+ 4db m=128 bits 12.5% mark density <100 consecutive zeroes i.431 level detect range is -18 to -30 db. i.431 00111 ? 01101 -18 ? -30 - 01110 ? 10001 ? 10101 10110-11111 -32 ? -38 ? -46 -48 0=e1 0 - 00000 ? 00010 -4 ? -8 level < q n=32 bits level > q+ 4db m=32 bits 12.5% mark density <16 consecutive zeroes g.775 level detect range is -9 to -35 db. g.775 00011 ? 10000 -10 ? -36 - 10001 ? 10101(default) 10110-11111 -38 ? -46 -48 1 - 00000 -4 level < q n=2048 bits level > q+ 4db m=32 bits 12.5% mark density <16 consecutive zeroes i.431 level detect range is -6 to -20 db. i.431/ etsi 00001 ? 01000 -6 ? -20 - 01001 ? 10101(default) 10110-11111 -22 ? -46 -48
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 30 february 5, 2009 3.4 transmit and detect internal patterns the internal patterns (all ones, all zeros, prbs/qrss pattern and activate/deactivate loopback code) wi ll be generated and detected by the idt82p5088. tclkn is used as the refe rence clock by default. mclk can also be used as the reference cl ock by setting the patt_clk bit ( maint1, 2ch... ) to ?1?. if the patt_clk bit ( maint1, 2ch... ) is set to ?0? and the patt[1:0] bits ( maint1, 2ch... ) are set to ?00?, the transmit path will operate in normal mode. 3.4.1 transmit all ones in transmit direction, the all ones data can be inserted into the data stream when the patt[1:0] bits ( maint1, 2ch... ) are set to ?01?. the trans- mit data stream is output from ttipn/ tringn. in this case, either tclkn or mclk can be used as the transmit clock, as selected by the patt_clk bit ( maint1, 2ch... ). 3.4.2 transmit all zeros if the patt_clk bit ( maint1, 2ch... ) is set to ?1?, the all zeros will be inserted into the transmit data stream when the patt[1:0] bits ( maint1, 2ch... ) are set to ?00?. 3.4.3 prbs/qrss generation and detection a prbs/qrss will be generated in the transmit direction and detected in the receive direction by idt82p5088. the qrss is 2 20 -1 for t1/j1 appli- cations and the prbs is 2 15 -1 for e1 applications, with maximum zero restrictions according to the at&t tr62411 and itu-t o.151. when the patt[1:0] bits ( maint1, 2ch... ) are set to ?10?, the prbs/ qrss pattern will be inserted into t he transmit data stream with the msb first. the prbs/qrss pattern will be transmitted directly or invertedly. the prbs/qrss in the received data st ream will be monitored. if the prbs/qrss has reached synchroniz ation status, the prbs_s bit ( stat0, 36h... ) will be set to ?1?, even in the presence of a logic error rate less than or equal to 10 -1 . the criteria for setting/clearing the prbs_s bit are shown in table-22 . prbs data can be inverted through setting the prbs_inv bit ( maint1, 2ch... ). any change of prbs_s bit will be captured by prbs_is bit ( ints0, 3ah... ). the prbs_ies bit ( intes, 35h... ) can be used to determine whether the ?0? to ?1? change of prbs_ s bit will be captured by the prbs_is bit or any changes of prbs_s bit will be captured by the prbs_is bit. when the prbs_is bit is ?1?, an interrupt will be generated if the prbs_ie bit ( intenc0, 33h... ) is set to ?1?. the received prbs/qrss logic errors can be counted in a 16-bit counter if the err_sel [1:0] bits ( maint6, 31h... ) are set to ?00?. refer to refer to 3.6 error detection/counting and insertion for the operation of the error counter. table-21 ais condition itu g.775 for e1 (lac bit is set to ?0? by default) etsi 300233 for e1 (lac bit is set to ?1?) ansi t1.231 for t1/j1 ais detected less than 3 zeros contained in each of two consecutive 512-bit streams are received less than 3 zeros contained in a 512-bit stream are received less than 9 zeros contained in an 8192-bit stream (a ones density of 99.9% over a period of 5.3ms) ais cleared 3 or more zeros contained in each of two consecutive 512-bit streams are received 3 or more zeros contained in a 512-bit stream are received 9 or more zeros contained in an 8192-bit stream are received table-22 criteria for setti ng/clearing the prbs_s bit prbs/qrss detection 6 or less than 6 bit errors detected in a 64 bits hopping window. prbs/qrss missing more than 6 bit errors detected in a 64 bits hopping window.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 31 february 5, 2009 3.5 loopback to facilitate testing and diagnosis, t he idt82p5088 provides four dif- ferent loopback configurations : analog loopback, digital loopback, remote loopback and inband loopback. 3.5.1 analog loopback when the alp bit ( maint0, 2bh... ) is set to ?1?, the corresponding chan- nel is configured in analog loopback mode. in this mode, the transmit sig- nals are looped back to the receiver in ternal termination in the receive path then output from rclkn, rdn, rd pn/rdnn. the all-ones pattern can be generated during analog loopback. at t he same time, the transmit sig- nals are still output to ttipn/tringn in transmit direction. figure-14 shows the process. the thz bit ( tcf1, 23h... ) shall be set to ?0? in analog loop- back mode. 3.5.2 digital loopback when the dlp bit ( maint0, 2bh... ) is set to ?1?, the corresponding chan- nel is configured in digital loopback m ode. in this mode, the transmit sig- nals are looped back to the jitter attenuator (if enabled) and decoder in receive path, then output from rclkn, rdn, rdpn/rdnn. at the same time, the transmit signals are still output to ttipn/tringn in transmit direc- tion. figure-15 shows the process. both analog loopback mode and digital loopback mode allow the sending of the internal patterns (all o nes, all zeros, prbs, etc.) which will overwrite the transmit signals. in this case, either tclkn or mclk can be used as the reference clock for internal patterns transmission. 3.5.3 remote loopback when the rlp bit ( maint0, 2bh... ) is set to ?1?, the corresponding chan- nel is configured in remote loopback mode. in this mode, the recovered clock and data output from clock and data recovery on the receive path is looped back to the jitter attenuator (if enabled) and waveform shaper in transmit path. figure-16 shows the process. figure-14 analog loopback figure-15 digital loopback one of the eight identical channels b8zs/ hdb3/ami encoder jitter attenuator line driver waveform shaper/lbo b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery transmitter internal termination receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn analog loopback one of the eight identical channels b8zs/ hdb3/ami encoder jitter attenuator b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery digital loopback receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn line driver waveform shaper/lbo transmitter internal termination
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 32 february 5, 2009 figure-16 remote loopback one of the eight identical channels b8zs/ hdb3/ami encoder jitter attenuator b8zs/ hdb3/ami decoder jitter attenuator data slicer adaptive equalizer los/ais detector clock and data recovery receiver internal termination tclkn tdnn tdn/tdpn rclkn cvn/rdnn losn rdn/rdpn rringn ttipn tringn rtipn remote loopback line driver waveform shaper/lbo transmitter internal termination
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 33 february 5, 2009 3.5.4 inband loopback when patt[1:0] bits ( maint1, 2ch... ) are set to ?11?, the correspond- ing channel is configured in inband loopbac k mode. in this mode, an acti- vate/deactivate loopback code is generated repeatedly in transmit direction per ansi t1. 403 which overwr ite the transmit signals. in receive direction, the code is detected per ansi t1. 403, even in the presence of 10 -2 bit error rate. if the automatic remote loopback is enabled by setting arlp bit ( maint0, 2bh... ) to ?1?, the chip will establish/demolish the remote loop- back based on the reception of the activate loopback code/deactivate loopback code for 5.1 s. if the arlp bit ( maint0, 2bh...) is set to ?0?, the remote loopback can also be demolished forcedly. 3.5.4.1 transmit activate/deactivate loopback code the pattern of the transmit activate/deactivate loopback code is defined by the tnlp[7:0] bits ( maint3, 2eh... ). whether the code repre- sents an activate loopback code or a deactivate loopback code is judged by the far end receiver. the length of the pattern ranges from 5 bits to 8 bits, as selected by the tnlp_l[1:0] bits ( maint2, 2dh... ). the pattern can be programmed to 6-bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4-bit-long. when the patt[1:0] bits ( maint1, 2ch... ) are set to ?11?, the transmission of the activate/deactivate loopback code is initiated. if the patt_clk bit ( maint1, 2ch... ) is set to ?0? and the patt[1:0] bits ( maint1, 2ch... ) are set to ?00?, the transmission of the acti- vate/deactivate loopback code will stop. the local transmit activate/deacti vate code setting should be the same as the receive code setting in the remote end. it is the same thing for the other way round. 3.5.4.2 receive activate/deactivate loopback code the pattern of the receive acti vate loopback code is defined by the rnlpa[7:0] bits ( maint4, 2fh... ). the length of this pattern ranges from 5 bits to 8 bits, as selected by the rnlpa_l [1:0] bits ( maint2, 2dh... ). the pattern can be programmed to 6-bi t-long or 8-bit-l ong respectively by repeating itself if it is 3-bit-long or 4-bit-long. the pattern of the receive deactivate loopback code is defined by the rnlpd[7:0] bits ( maint5, 30h... ). the length of the receive deactivate loopback code ranges from 5 bits to 8 bits, as selected by the rnlpd_l[1:0] bits ( maint2, 2dh... ). the pattern can be programmed to 6-bit-long or 8-bit-long respec tively by repeating itself if it is 3-bit-long or 4- bit-long. after the activate loopback code has been detected in the receive data for more than 30 ms (in e1 mode) / 40 ms (in t1/j1 mode), the nlpa_s bit ( stat0, 36h... ) will be set to ?1? to declare the reception of the activate loopback code. after the deactivate loopback code has been detected in the receive data for more than 30 ms (in e1 mode) / 40 ms (in t1/j1 mode), the nlpd_s bit ( stat0, 36h... ) will be set to ?1? to declare the reception of the deactivate loopback code. when the nlpa_ies bit ( intes, 35h... ) is set to ?0?, only the ?0? to ?1? transition of the nlpa_s bit will generate an interrupt and set the nlpa_is bit ( ints0, 3ah... ) to ?1?. when the nlpa_ies bit is set to ?1?, any changes of the nlpa_s bit will generate an interrupt and set the nlpa_is bit ( ints0, 3ah... ) to ?1?. the nlpa_is bit will be reset to ?0? after being read. when the nlpd_ies bit ( intes, 35h... ) is set to ?0?, only the ?0? to ?1? transition of the nlpd_s bit will generate an interrupt and set the nlpd_is bit ( ints0, 3ah... ) to ?1?. when the nlpd_ies bit is set to ?1?, any changes of the nlpd_s bit will generate an interrupt and set the nlpd_is bit ( ints0, 3ah... ) to ?1?. the nlpd_is bit will be reset to ?0? after being read. 3.5.4.3 automatic remote loopback when arlp bit ( maint0, 2bh...) is set to ?1?, the corresponding chan- nel is configured into the automatic remote loopback mode. in this mode, if the activate loopback code has been detected in the receive data for more than 5.1 s, the remote loopback (shown as figure-16 ) will be estab- lished automatically, and the arlp_s bit ( stat0, 36h... ) will be set to ?1? to indicate the establishment of the remote loopback. the nlpa_s bit ( stat0, 36h... ) is set to ?1? to generate an interrupt. in this case, the remote loopback mode will still be kept even if the receiver stop receiving the acti- vate loopback code. if the deactivate loopback code has been detected in the receive data for more than 5.1 s, the remote loopback will be demolished automatically, and the arlp_s bit ( stat0, 36h... ) will set to ?0? to indicate the demolish- ment of the remote loopback. the nlpd_s bit ( stat0, 36h... ) is set to ?1? to generate an interrupt. the remote loopback can also be demolished forcedly by setting arlp bit ( maint0, 2bh...) to ?0?.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 34 february 5, 2009 3.6 error detection/co unting and insertion 3.6.1 definition of line coding error the following line encoding errors can be detected and counted by the idt82p5088: ? received bipolar violation (bpv) error: in ami coding, when two consecutive pulses of the same pol arity are received, a bpv error is declared. ? hdb3/b8zs code violation (cv) error: in hdb3/b8zs coding, a cv error is declared when tw o consecutive bpv errors are detected, and the pulses that have the same polarity as the previ- ous pulse are not the hdb3/b8zs zero substitution pulses. ? excess zero (exz) error: there are two standards defining the exz errors: ansi and fcc. the exz_def bit ( maint6, 31h... ) chooses which standard will be adopted by the corresponding channel to judge the exz error. table-23 shows definition of exz. 3.6.2 error detection and counting which type of the receiving errors (received cv/bpv errors, excess zero errors and prbs logic errors ) will be counted is determined by err_sel[1:0] bits ( maint6, 31h... ). only one type of receiving error can be counted at a time except that when the err_sel[1:0] bits are set to ?11?, both cv/bpv and exz errors will be detected and counted. the receiving errors are counted in an internal 16-bit error counter. once an error is detected, an error in terrupt which is indicated by corre- sponding bit in ( ints1, 3bh... ) will be generated if it is not masked. this error counter can be operated in two modes: auto report mode and man- ual report mode, as selected by the cnt_md bit ( maint6, 31h... ). in sin- gle rail mode, once bpv or cv errors are detected, the cvn pin will be driven to high for one rclk period. ? auto report mode in auto report mode, the internal c ounter starts to count the received errors when the cnt_md bit ( maint6, 31h... ) is set to ?1?. a one-second timer is used to set the counting per iod. the received errors are counted within one second. if the one-second timer expires, the value in the internal counter will be transferred to ( cntl, 3ch... ) and ( cnth, 3dh... ), then the internal counter will be reset and start to count received errors for the next second. the errors occurred during the transfer will be accumulated to the next round. the expiration of the one- second timer will set tmov_is bit ( ints1, 3bh... ) to ?1?, and will generate an interrupt if the timer_ie bit ( intenc1, 34h... ) is set to ?0?. the cv_is bit ( ints1, 3bh... ) will be cleared after the interrupt register is read. the content in the ( cntl, 3ch... ) and ( cnth, 3dh... ) should be read within the next second. if the counter over- flows, a counter overflow interrupt which is indicated by cnt_ov_is bit ( ints1, 3bh... ) will be generated if it is not masked by cnt_ie bit ( intenc1, 34h... ). figure-17 auto report mode table-23 exz definition exz definition ansi fcc ami more than 15 consecutive 0s are detected more than 80 consecutive 0s are detected hdb3 more than 3 consecutive 0s are detected more than 3 consecutive 0s are detected b8zs more than 7 consecutive 0s are detected more than 7 consecutive 0s are detected one-second timer expired? counting auto report mode (cnt_md=1) bit tmov_is is set to '1' y n cntl, cnth data in counter counter 0 read the data in cntl, cnth within the next second next second repeats the same process bit tmov_is is cleared after the interrupt register is read
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 35 february 5, 2009 ? manual report mode in manual report mode, the internal error counter starts to count the received errors when the cnt_md bit (maint6, 31h...) is set to ?0?. when there is a ?0? to ?1? trans ition on the cnt_stop bit (maint6, 31h...) , the data in the counter will be transferred to (cntl, 3ch...) and (cnth, 3dh...) , then the counter will be reset. t he errors occurred during the trans- fer will be accumulated to the next r ound. if the counter overflows, a counter overflow interrupt indica ted by cntov_is bit (ints1, 3bh...) will be gen- erated if it is not masked by cnt_ie bit (intenc1, 34h...) . figure-18 manual report mode note: 1. it is recommended that users should do the followings within next round of error counting: read the data in cntl and cnth; reset cnt_trf bit for the next ?0? to ?1? transition on this bit. 3.6.3 bipolar violation and prbs error insertion only when three consecutive ?1?s are detected in the transmit data stream, will a ?0? to ?1? transition on the bpv_ins bit ( maint6, 31h... ) gen- erate a bipolar violation pulse, and the polarity of the second ?1? in the series will be inverted. a ?0? to ?1? transition on the eer_ins bit ( maint6, 31h... ) will generate a logic error during the prbs/qrss transmission. 3.7 line driver failure monitoring the transmit driver failure monito r can be enabled or disabled by setting dfm_off bit ( tcf1, 23h... ). if the transmit driv er failure monitor is enabled, the transmit driver failur e will be captured by df_s bit ( stat0, 36h... ). the transition of the df_s bit is reflected by df_is bit ( ints0, 3ah... ), and, if enabled by df_ie bit ( intenc0, 33h... ), will generate an interrupt. when there is a short circ uit on the ttipn/tringn port, the output current will be limited to 100 ma (typ ical) and an interrupt will be generated. a '0' to '1' transition on cnt_stop? counting manual report mode (cnt_md=0) cntl, cnth data in counter counter 0 y n next round repeat the same process read the data in cntl, cnth within next round 1 reset cnt_stop for the next '0' to '1' transition
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 36 february 5, 2009 3.8 clock generator and tclk 3.8.1 clock generator figure-19 clock generator the osci pin is connected to an exter nal crystal oscillator. in t1 mode e1 rate of transmit system interfac e, this clock must keep the crystal oscillator same with system transmit clock (tsckn/mtsck). the osco pin outputs the inverted, buffered clock input from osci. the clock frequency of osci is defined by clk_sel[2:0]. refer to table-24 . the clk_gen_1.544 pin outputs the 1.544 mhz clock signal and the clk_gen_2.048 outputs the 2.048 mhz clock signal. the frequecy of the refa_out/r efb_out pins is 2.048 mhz (e1) or 1.544 mhz (t1/j1). when no los is detected, the refa_out/ refb_out pins output a recovered cl ock from the clock and data recov- ery function block of one of the eight links. the refa_out link is selected by the ro1[2:0] bits (b2~0, t1/j1- 007h / b2~0, e1-007h); the refb_out link is selected by the ro2[2:0] bits (b5~3, t1/j1-007h / b5~3, e1-007h). when los is detected, the refa_o ut/refb_out pins output mclk or high level, as selected by the refh_los bit (b0, t1/j1-03eh,... / b0, e1- 03eh,...). * note: mclk is a clock derived from osci using an internal pll, and the frequency is 2.048 mhz (e1) or 1.544 mhz (t1/j1). 3.8.2 transmit clock (tclk) the tclkn is used to sample the transmit data on tdn/tdpn, tdnn. the active edge of tclkn can be selected by the tclk_sel bit ( tcf0, 22h... ). during transmit all ones, prbs/qrss patterns or inband loop- back code, either tclkn or mclk can be used as the reference clock. this is selected by the patt_clk bit ( maint1, 2ch... ). but for automatic transmit all ones and ais, only mclk is used as the reference clock and the patt_clk bit is ignored. in automatic transmit all ones condition, the atao bit ( maint1, 2ch ) is set to ?1?. in ais condi- tion, the raise bit ( maint1, 2ch ) is set to ?1?. if tclkn has been missing for more than 70 mclk cycles, tclk_los bit ( stat0, 36h... ) will be set, and the corresponding ttipn/tringn will become high impedance if this channel is not used for remote loopback or is not using mclk to transmit internal patterns (taos, all zeros, prbs and in-band loopback code). when tclkn is detected again, tclk_los bit ( stat0, 36h... ) will be cleared. the reference frequency to detect a tclkn loss is derived from mclk. figure-20 tclk operation flowchart table-24 reference clock selection clk_sel[2:0] input clock signal (mhz) 000 1 x 1.544 001 2 x 1.544 010 3 x 1.544 011 4 x 1.544 100 1 x 2.048 101 2 x 2.048 110 3 x 2.048 111 4 x 2.048 clock generator clk_gen_1.544 crystal oscillator clk_sel[2:0] osci osco clk_gen_2.048 refa_out refb_out normal operation mode transmitter n enters high impedance status and generates transmit clock loss interrupt if not masked tclkn status? clocked l/h mclk=h/l? all transmitters high impedance status yes clocked
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 37 february 5, 2009 3.9 microprocessor interface the microprocessor interface provi des access to read and write the registers in the device. the interface consists of serial peripheral inter- face (spi) and parallel microprocessor interface. 3.9.1 spi mode pull the spien pin to high, and the microprocessor interface will be set in spi mode. in this mode, only the cs , sclk, sdi and sdo pins are interfaced with the microprocessor. a falling transition on cs pin indicates the start of a read/write operation, and a rising transition indicates the end of the operation. after the cs pin is set to low, two bytes include instruction and address bytes on the sdi pin are input to the device on the rising edge of the sclk pin. first byte consists of one instruction bit at msb and three address bits at lsb, and the second byte is low 8 address bits. if the msb is ?1?, it is read operation. if the msb is ?0?, it is write operation. if the device is in read oper ation, the data read from the spec- ified register is output on the sdo pin on the falling edge of the sclk (refer to figure 21 ). if the device is in write operation, the data written to the specified register is input on the sdi pin following the address byte (refer to figure 22 ). figure-21 read operation in spi mode figure-22 write operation in spi mode 3.9.2 parallel microprocessor interface pull the spien pin to low, the mi croprocessor interface will be set in parallel mode. in this mode, the interf ace is compatible with the motorola and the intel microprocessor, which is selected by the mpm pin. the idt82p5088 uses separate address bus and data bus. the mode selec- tion and the interfaced pin are tabularized in table 25 . cs sclk sdi sdo 10 1 2 3 4 5 6 7 8 9 11121314151617181920212223 a0 a7 a6 a5 a4 a3 a2 a1 instruction register address high impedance d0 d7 d6 d5 d4 d3 d2 d1 don't care a9 xxxa11a10 a8 0 cs sclk sdi sdo 10 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 a0 a7 a6 a5 a4 a3 a2 a1 instruction data byte high impedance d0 d7 d6 d5 d4 d3 d2 d1 register address a8 xxxa11a10a9 table-25 parallel microprocessor interface pin mpm microprocessor interface interfaced pin low motorola cs , ds , r w , a[10:0], d[7:0] high intel cs , rd , wr , a[10:0], d[7:0]
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 38 february 5, 2009 3.10 interrupt handling an active level on the int pin represents an interrupt of the idt82p5088. the int_ch[7:0] bits ( intch, 09h ) should be read to identify which chan- nel(s) generate the interrupt. the interrupt event is captured by the corresponding bit in the interrupt status register (ints0, 3ah...) or (ints1, 3bh...) . every kind of interrupt can be enabled/disabled individually by the corresponding bit in the register (intenc0, 33h...) or (intenc1, 34h...) . some event is reflected by the corresponding bit in the status register (stat0, 36h... ) or (stat1, 37h...) , and the interrupt trigger edge selection register can be used to determine how the status register sets the inte rrupt status register. after the interrupt status register (ints0, 3ah...) or (ints1, 3bh...) is read, the corresponding bit indicating which channel generates the inter- rupt in the intch register ( 09h ) will be reset. only when all the pending interrupt is acknowledged through readi ng the interrupt status registers of all the channels (ints0, 3ah...) or (ints1, 3bh...) will all the bits in the intch register ( 09h ) be reset and the int pin become inactive. there are totally fourteen kinds of events that could be the interrupt source for one channel: (1).los detected (2).ais detected (3).driver failure detected (4).tclk loss (5).synchronization status of prbs (6).prbs error detected (7).code violation received (8).excessive zeros received (9).ja fifo overflow/underflow (10).inband loopback code status (11).equalizer out of range (12).one-second timer expired (13).error counter overflow (14).arbitrary waveform generator overflow table-26 is a summary of all kinds of interrupt and their associated sta- tus bit, interrupt status bit, interrupt trigger edge selection bit and interrupt mask bit. table-26 interrupt event interrupt event status bit (stat0, stat1) interrupt status bit (ints0, ints1) interrupt edge selection bit (intes) interrupt mask bit (intenc0, intenc1) los detected los_s los_is los_ies los_ie ais detected ais_s ais_is ais_ies ais_ie driver failure detected df_s df_is df_ies df_ie tclkn loss tclk_los tclk_los_is tclk_ies tclk_ie synchronization status of prbs/qrss prbs_s prbs_is prbs_ies prbs_ie prbs/qrss error err_is err_ie code violation received cv_is cv_ie excessive zeros received exz_is exz_ie ja fifo overflow jaov_is jaov_ie ja fifo underflow jaud_is jaud_ie equalizer out of range eq_s eq_is eq_ies eq_ie inband loopback activate code status nlpa_s nlpa_is nlpa_ies nlpa_ie inband loopback deactivate code status nlpd_s nlpd_is nlpd_ies nlpd_ie one-second timer expired tmov_is timer_ie error counter overflow cnt_ov_is cnt_ie arbitrary waveform generator overflow dac_ov_is dac_ov_ie
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter functional des cription 39 february 5, 2009 3.11 general purpose i/o the idt82p5088 provides two general purpose digital i/o pins: gpio1, gpio0. these two pins can be consi dered as digital input or output port by the dir1 bit ( gpio, 06h ) and dir0 bit ( gpio, 06h ) respectively. if the gpio1 and gpio0 are configured as input port, the level1 bit ( gpio, 06h ) and the level0 bit ( gpio, 06h ) are used to reflect the level of the gpio1 pin and the gpio0 pin respectively. if the gpio1 and gpio0 are configured as output port, the content in the level1 bit and level0 bit determines the logic value of gpio 1 pin and gpio0 pin respectively. 3.12 reset operation the chip can be reset in two ways: ? software reset: writing to the rst register ( 04h ) will reset the chip in 1 us. ? hardware reset: asserting the reset pin low for a minimum of 100 ns will reset the chip. during hardware reset, the device requires an active clock on mclk. for t1/j1 operation, bit te_mode( t1e1 mode, 20h... ) is set after reset. before accessing any other regi sters a delay of 50 us is required to allow the internal clocking to be settled. after reset, all drivers output are in high impedance state, all the internal flip-flops are reset, and all the regist ers are initialized to default values. when performing a software reset, the te_mode bit ( t1e1 mode, 20h... ) will not be reset and stay with the set value. 3.13 power supply this chip uses 3.3 v and 1.8 v power supply.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 40 february 5, 2009 4 programming information 4.1 register list and map the idt82p5088 registers can be di vided into global registers and local registers. the operation on the global registers affects all the eight channels while the operation on local r egisters only affects that specific channel. for different channel, the address of local register is different. table-27 is the map of global registers and table-28 is the map of local registers. 4.2 reserved registers when writing to registers with rese rved bit locations, the default state must be written to the reserved bi ts to ensure proper device operation. table-27 global register list and map address (hex) register r/w map b7 b6 b5 b4 b3 b2 b1 b0 000 ~ 001 reserved 002 id r id7 id6 id5 id4 id3 id2 id1 id0 003 reserved 004rstw -------- 005 mon r/w - - - - mon3 mon2 mon1 mon1 006 gpio r/w - - - - level1 level0 dir1 dir0 007 refout r/w - - ro22 ro21 ro20 ro12 ro11 ro10 008 reserved 009 intch r int_ch7 int_ch6 int_ch5 in t_ch4 int_ch3 int_ch2 int_ch1 int_ch0 00a ~00b reserved 00c timer inte r/w tmovie 00d timer ints r/w tmovis 00e ~ 016 reserved
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 41 february 5, 2009 * note: in the ?address? column, the ?x? represents 0 ~ 7 corresponding to the eight links. table-28 per channel register list and map address (hex) register r/w map ch1-ch8 b7 b6 b5 b4 b3 b2 b1 b0 x20* t1e1 mode - - - - - - - temode transmit path control registers x21 tjacf r/w - - tjitt_test tja_li mit tja_e tja_dp1 tja_dp0 tja_bw x22 tcf0 r/w - - - t_off td_inv tclk_sel t_md1 t_md0 x23 tcf1 r/w - - dfm_off thz puls3 puls2 puls1 puls0 x24 tcf2 r/w - - scal5 scal4 scal3 scal2 scal1 scal0 x25 tcf3 r/w done rw ui1 ui0 samp3 samp2 samp1 samp0 x26 tcf4 r/w - wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 receive path control registers x27 rjacf r/w - - rjitt_test rja_limit rja_e rja_dp1 rja_dp0 rja_bw x28 rcf0 r/w - - - r_off rd_inv rclk_sel r_md1 r_md0 x29 rcf1 r/w - eq_on fixg los4 los3 lo s2 los1 los0 x2a rcf2 r/w - - slice1 slice0 updw1 updw0 mg1 mg0 network diagnostics control registers x2b maint0 r/w - - - - arlp rlp alp dlp x2c maint1 r/w - patt1 patt0 patt_clk prbs_inv lac raise atao x2d maint2 r/w - - tnlp_l1 tnlp_l0 rnlpa_l1 rnlpa_l0 rnlpd_l1 rnlpd_l0 x2e maint3 r/w tnlp7 tnlp6 tnlp5 tnlp4 tnlp3 tnlp2 tnlp1 tnlp0 x2f maint4 r/w rnlpa7 rnlpa6 rnlpa5 rnlpa4 rnlpa3 rnlpa2 rnlpa1 rnlpa0 x30 maint5 r/w rnlpd7 rnlpd6 rnlpd5 rnlpd4 rnlpd3 rnlpd2 rnlpd1 rnlpd0 x31 maint6 r/w - bpv_ins err_ins exz_d ef err_sel1 err_sel0 cnt_md cnt_stop transmit and receive termination registers x32 term r/w - - t_term2 t_term1 t_term0 r_term2 r_term1 r_term0 interrupt control registers x33 intenc0 r/w - nlpa_ie nlpd_ie prbs_ie tclk_ie df_ie ais_ie los_ie x34 intenc1 r/w - dac_ie tja_ie rj a_ie err_ie exz_ie cv_ie cnt_ie x35 intes r/w - nlpa_ies nlpd_ies prbs_ ies tclk_ies df_ies ais_ies los_ies line status registers x36 stat0 r arlp_s nlpa_s nlpd_s p rbs_s tclk_los df_s ais_s los_s x37 stat1 r - - - latt4 latt3 latt2 latt1 latt0 x38 tjitt r - tjitt6 tjitt5 tjitt4 tjitt3 tjitt2 tjitt1 tjitt0 x39 rjitt r - rjitt6 rjitt5 rjit t4 rjitt3 rjitt2 rjitt1 rjitt0 interrupt status registers x3a ints0 r/w - nlpa_is nlpd_is prbs_is tclk_los_is df_is ais_is los_is x3b ints1 r/w - dac_is tja_is rja_is err_is exz_is cv_is cntov_is counter registers x3c cntl r cnt_l7 cnt_l6 cnt_l5 cnt_ l4 cnt_l3 cnt_l2 cnt_l1 cnt_l0 x3d cnth r cnl_h15 cnl_h14 cnl_h13 cnl_h12 cnl_h11 cnl_h10 cnl_h9 cnl_h8 x3e refc r/w - - - - - - - refh_los
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 42 february 5, 2009 4.3 register description 4.3.1 global registers table-29 id: chip revision register (r, address = 02h) symbol bit default description id[7:0] 7-0 01h current silicon chip id. table-30 rst: reset register (w, address = 04h) symbol bit default description rst[7:0] 7-0 01h software reset. a write operation on this register will reset all internal registers to their default values, and the sta- tus of all ports are set to the default status. the content in this register can not be changed. after reset, all drivers output are in high impedance state. note: bit t1e1 ( gcf0, 20h ) will keep set value and will not be reset. table-31 mon: g.772 monitor control register (r/w, address = 05h) symbol bit default description -7-40reserved mon[3:0] 3-0 0000 mon selects the transmitter or receiver channel to be monitored. = 0000: receiver 1 is in normal operation without monitoring = 0001: monitor receiver 2 = 0010: monitor receiver 3 = 0011: monitor receiver 4 = 0100: monitor receiver 5 = 0101: monitor receiver 6 = 0110: monitor receiver 7 = 0111: monitor receiver 8 = 1000: transmitter 1 is in normal operation without monitoring = 1001: monitor transmitter 2 = 1010: monitor transmitter 3 = 1011: monitor transmitter 4 = 1100: monitor transmitter 5 = 1101: monitor transmitter 6 = 1110: monitor transmitter 7 = 1111: monitor transmitter 8 table-32 gpio: general purpose io pin definition register (r/w, address = 06h) symbol bit default description - 7-4 0000 reserved. level1 3 - when gpio1 is defined as an output port, this bit determines the output level on gpio1 pin. = 0: low level output on port gpio1 = 1: high level output on port gpio1 when gpio1 is defined as an input port, this bit reflects the input level of gpio1 pin. = 0: low level input on port gpio1 = 1: high level input on port gpio1
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 43 february 5, 2009 level0 2 - when gpio0 is defined as an output port, this bit determines the output level on gpio0 pin. = 0: low level output on port gpio0 = 1: high level output on port gpio0 when gpio0 is defined as an input port, this bit reflects the input level on gpio0 pin = 0: low level input on port gpio0 = 1: high level input on port gpio0 dir1 1 1 = 0: port gpio1 is configured as output port = 1: port gpio1 is configured as input port dir0 0 1 = 0: port gpio0 is configured as output port = 1: port gpio0 is configured as input port table-33 refout: reference clock output select register (r/w, address = 07h) symbol bit default description - 7-6 00 reserved ro2[2:0] 5-3 000 = 000: rclk1 internally loop to refa output pin = 001: rclk2 internally loop to refa output pin = 010: rclk3 internally loop to refa output pin = 011: rclk4 internally loop to refa output pin = 000: rclk5 internally loop to refa output pin = 101: rclk6 internally loop to refa output pin = 110: rclk7 internally loop to refa output pin = 111: rclk8 internally loop to refa output pin ro1[2:0] 2-0 000 = 000: rclk1 internally loop to refb output pin = 001: rclk2 internally loop to refb output pin = 010: rclk3 internally loop to refb output pin = 011: rclk4 internally loop to refb output pin = 100: rclk5 internally loop to refb output pin = 101: rclk6 internally loop to refb output pin = 110: rclk7 internally loop to refb output pin = 111: rclk8 internally loop to refb output pin table-34 intch: interrupt channel in dication register (r, address = 09h) symbol bit default description int_ch[7:0] 7-0 00h int_ch[n]=1 indicates that an interrupt was generated by channel [n+1] respectively. table-35 timer inte: timer interrupt enable register (r, address = 0ch) symbol bit default description - 7-1 000000 reserved. tmovie 0 0 = 0: mask interrupt = 1: enable timer over interrupt table-32 gpio: general purpose io pin definition register (continued) (r/w, address = 06h) symbol bit default description
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 44 february 5, 2009 4.3.2 per channel control registers 4.3.3 transmit path control registers table-36 timer ints: timer interrupt status register (bit tmov_is is reset after writing a 1 into this bit position) (r, address = 0dh) symbol bit default description - 7-1 000000 reserved. tmovis 0 0 indicate one second timer whether is over or not. = 0: one second timer is not over since last reset tmovis. = 1: one second timer is over and generate an interrupt request if no masked. table-37 tie1 mode: t1 or e1 mode select register (r/w, address = x20h) symbol bit default description - 7-1 000000 reserved temode 0 0 this bit selects the operating mode for the current link. = 0: e1 mode is selected. = 1: t1/j1 mode is selected. table-38 tjacf: jitter attenuator configuration register for transmit path (r/w, address = x21h) symbol bit default description - 7-6 00 reserved tjitt_test 5 0 this bit sele cts jitter measure mode = 0: real time mode (update jitter measuring value each received clock cycle) = 1: accumulation mode (measuring p-p value of jitter since last read) tja_limit 4 1 wide jitter attenuation bandwidth = 0: normal mode = 1: ja limit mode tja_e 3 00 jitter attenuator configuration = 0: ja not used = 1: ja enabled tja_dp[1:0] 2-1 00 jitter attenuator depth selection = 00: 128 bits = 01: 64 bits = 10/11: 32 bits tja_bw 0 0 jitter transfer function bandwidth selection jabw t1/j1 e1 0 5 hz 6.77 hz 1 1.26 hz 0.87 hz table-39 tcf0: transmitter configuration register 0 for transmit path (r/w, address = x22h) symbol bit default description - 7-5 000 reserved
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 45 february 5, 2009 1. in internal impedance matching mode, for e1/75 ? cable impedance, the puls[3:0] bits ( tcf1, x23h ) should be set to ?0000?. in external impedance matching mode, for e1/75 ? cable impedance, the puls[3:0] bits should be set to ?0001?. t_off 4 0 transmitter power down enable = 0: transmitter power up = 1: transmitter power down and line driver high impedance td_inv 3 0 transmit data invert = 0: data on tdn or tdpn/tdnn is active high = 1: data on tdn or tdpn/tdnn is active low tclk_sel 2 0 transmit clock edge select = 0: data on tdn or tdpn/tdnn is sampled on the falling edges of tclkn = 1: data on tdn or tdpn/tdnn is sampled on the rising edges of tclkn t_md[1:0] 1-0 00 transmitter operation mode control bits which select different stages of transmit data path = 00: enable hdb3/b8zs encoder and waveform shaper blocks, input on tdn is single rail nrz data = 01: enable ami encoder and waveform shaper blocks, input on pin tdn is single rail nrz data = 1x: encoder is bypassed, dual rail nrz transmit data input on pin tdpn/tdnn table-40 tcf1: transmitter configuration register 1 for transmit path (r/w, address = x23h) symbol bit default description - 7-6 00 reserved. this bit should be ?0? for normal operation. dfm_off 5 0 transmit driver failure monitor disable = 0: dfm is enabled = 1: dfm is disabled thz 4 1 transmit line driver high impedance enable = 0: normal state = 1: transmit line driver high impedance enable (other transmit path still in normal state) puls[3:0] 3-0 0000 these bits select the transmit template/lbo for short-haul/long-haul applications. t1/e1/j1 tclk cable impedance cable range or lbo cable loss 0000 1 e1 2.048 mhz 75 ? - 0~43 db (default) 0001 e1 2.048 mhz 120 ? -0~43 db 0010 dsx1 1.544 mhz 100 ? 0~133 ft 0~0.6 db 0011 dsx1 1.544 mhz 100 ? 133~266 ft 0.6~1.2 db 0100 dsx1 1.544 mhz 100 ? 266~399 ft 1.2~1.8 db 0101 dsx1 1.544 mhz 100 ? 399~533 ft 1.8~2.4 db 0110 dsx1 1.544 mhz 100 ? 533~655 ft 2.4~3.0 db 0111 j1 1.544 mhz 110 ? 0~655 ft 0~3.0 db 1000 ds1 1.544 mhz 100 ? 0 db lbo 0~36 db 1001 ds1 1.544 mhz 100 ? -7.5 db lbo 0~28.5 db 1010 ds1 1.544 mhz 100 ? -15 db lbo 0~21 db 1011 ds1 1.544 mhz 100 ? -22.5 db lbo 0~13.5 db 11xx user programmable waveform setting table-39 tcf0: transmitter configuration register 0 for transmit path (continued) (r/w, address = x22h) symbol bit default description
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 46 february 5, 2009 table-41 tcf2: transmitter configuration register 2 for transmit path (r/w, address = x24h) symbol bit default description - 7-6 00 reserved scal[5:0] 5-0 100001 scal specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses whic h is to be transmitted if needed. the default value of scal[5:0] is ?100001?. refer to 3.2.3.3 user-programmable arbi- trary waveform . = 110110: default value for t1 0~133 ft, t1 133~266 ft, t1 266~399 ft, t1 399~533 ft, t1 533~655 ft, j1 0~655 ft, ds1 0db lbo. one step change of this value results in 2% scaling up/down against the pulse amplitude. = 010001: default value for ds1 -7.5 db lbo. one step change of this value results in 6.25% scaling up/down against the pulse amplitude. = 001000: default value for ds1 -15.0 db lbo. one step change of this value results in 12.5% scaling up/down against the pulse amplitude. = 000100: default value for ds1 -22.5 db lbo. one step change of this value results in 25% scaling up/down against the pulse amplitude. = 100001: default value for e1 75 ? and 120 ? . one step change of this value results in 3% scaling up/down against the pulse amplitude. table-42 tcf3: transmitter configuration register 3 for transmit path (r/w, address = x25h) symbol bit default description done 7 0 after ?1? is written to this bit, a read or write operation is implemented. rw 6 0 this bit selects read or write operation = 0: write to ram = 1: read from ram ui[1:0] 5-4 00 these bits specify the unit interval address. there are 4 unit intervals. = 00: ui address is 0 (the most left ui) = 01: ui address is 1 = 10: ui address is 2 = 11: ui address is 3 samp[3:0] 3-0 0000 these bits specify the sample address. each ui has 16 samples. = 0000: sample address is 0 (the most left sample) = 0001: sample address is 1 = 0010: sample address is 2 ...... = 1110: sample address is 14 = 1111: sample address is 15 table-43 tcf4: transmitter configuration register 4 for transmit path (r/w, address = x26h) symbol bit default description -70reserved wdat[6:0] 6-0 0000000 in indirect write operation, the wdat[6:0] will be loaded to the pulse template ram, specifying the amplitud e of the sample. after an indirect read operation, the amplitude data of the sample in the pulse template ram will be output to the wdat[6:0].
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 47 february 5, 2009 4.3.4 receive path control registers table-44 rjacf: jitter attenuator configuration register for receive path (r/w, address = x27h) symbol bit default description - 7-6 00 reserved rjitt_test 5 0 this bit selects jitter measure mode = 0: real time mode (update jitter measuring value each received clock cycle) = 1: accumulation mode (measuring p-p value of jitter since last read) rja_limit 4 1 wide jitter attenuation bandwidth = 0: normal mode = 1: ja limit mode rja_e 3 00 jitter attenuator configuration = 0: ja not used = 1: ja enabled rja_dp[1:0] 2-1 00 jitter attenuator depth selection = 00: 128 bits = 01: 64 bits = 10/11: 32 bits rja_bw 0 0 jitter transfer function bandwidth selection jabw t1/j1 e1 0 5 hz 6.77 hz 1 1.26 hz 0.87 hz table-45 rcf0: receiver configuration register 0 for receive path (r/w, address = x28h) symbol bit default description - 7-5 000 reserved r_off 4 0 receiver power down enable = 0: receiver power up = 1: receiver power down rd_inv 3 0 receive data invert = 0: data on rdn or rdpn/rdnn is active high = 1: data on rdn or rdpn/rdnn is active low rclk_sel 2 0 receive clock edge select (this bit is ignored in slicer mode) = 0: data on rdn or rdpn/rdnn is updated on the rising edges of rclkn = 1: data on rdn or rdpn/rdnn is updated on the falling edges of rclkn r_md[1:0] 1-0 00 receiver path decoding selection = 00: receive data is hdb3 (e1) / b8zs (t1/j1) decoded and output on rdn with single rail nrz format = 01: receive data is ami decoded and output on rdn with single rail nrz format = 10: decoder is bypassed, re-timed dual rail data with nrz format output on rdpn/rdnn (dual rail mode with clock recovery) = 11: both cdr and decoder blocks are bypassed, slicer data with rz format output on rdpn/rdnn (slicer mode)
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 48 february 5, 2009 table-46 rcf1: receiver configuration register 1 for receive path (r/w, address = x29h) symbol bit default description -70reserved eq_on 6 0 = 0: receive equalizer off (short haul receiver) = 1: receive equalizer on (long haul receiver) fixg 5 0 select fix gain or los level detect threshold. note that this bit is effective only when long haul operation mode is selected (eq_on=1). = 0: the receiver operates in adaptive gain mode, in which the maximum receive sensitivity is up to 43 db for e1 and 36 db for t1. = 1: fixed gain mode. the receive sensitivity is fixed on the value selected by los[4:0]. los[4:0] 4-0 10101 los clear level (db) los declare level (db) 00000 0 <-4 00001 >-2 <-6 00010 >-4 <-8 00011 >-6 <-10 00100 >-8 <-12 00101 >-10 <-14 00110 >-12 <-16 00111 >-14 <-18 01000 >-16 <-20 01001 >-18 <-22 01010 >-20 <-24 01011 >-22 <-26 01100 >-24 <-28 01101 >-26 <-30 01110 >-28 <-32 01111 >-30 <-34 10000 >-32 <-36 10001 >-34 <-38 10010 >-36 <-40 10011 >-38 <-42 10100 >-40 <-44 10101 >-42 <-46 10110-11111 >-44 <-48
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 49 february 5, 2009 4.3.5 network diagnost ics control registers table-47 rcf2: receiver configuration register 2 for receive path (r/w, address = x2ah) symbol bit default description - 7-6 00 reserved slice[1:0] 5-4 01 receive slicer threshold = 00: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 40% of the peak amplitude. = 01: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 50% of the peak amplitude. = 10: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 60% of the peak amplitude. = 11: the receive slicer generates a mark if the voltage on rtipn/rringn exceeds 70% of the peak amplitude. updw[1:0] 3-2 10 equalizer observation window = 00: 32 bits = 01: 64 bits = 10: 128 bits = 11: 256 bits mg[1:0] 1-0 00 monitor gain setting: these bits select the internal linear gain boost = 00: 0 db = 01: 22 db = 10: 26 db = 11: 32 db table-48 maint0: maintenance function control register 0 (r/w, address = x2bh) symbol bit default description - 7-4 0000 reserved arlp 3 0 automatic remote loopback control = 0: disables automatic remote loopback (normal transmit and receive operation) = 1: enables automatic remote loopback rlp 2 0 remote loopback enable = 0: disables remote loopback (normal transmit and receive operation) = 1: enables remote loopback alp 1 0 analog loopback enable = 0: disables analog loopback (normal transmit and receive operation) = 1: enables analog loopback dlp 0 0 digital loopback enable = 0: disables digital loopback (normal transmit and receive operation) = 1: enables digital loopback table-49 maint1: maintenance function control register 1 (r/w, address = x2ch) symbol bit default description -70reserved patt[1:0] 6-5 00 these bits select the internal pattern and insert it into the transmit data stream. = 00: normal operation (patt_clk = 0) / insert all zeros (patt_clk = 1) = 01: insert all ones = 10: insert prbs (e1: 2 15 -1) or qrss (t1/j1: 2 20 -1) = 11: insert programmable inband loopback activate or deactivate code
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 50 february 5, 2009 patt_clk 4 0 selects reference clock for transmitting internal pattern = 0: uses tclkn as the reference clock = 1: uses mclk as the reference clock prbs_inv 3 0 inverts prbs = 0: prbs data is not inverted = 1: prbs data is inverted before transmission and detection lac 2 0 the los/ais criterion is selected as below: = 0: g.775 (e1) / t1.231 (t1/j1) = 1: etsi 300233 & i.431 (e1) / i.431 (t1/j1) raise 1 0 ais enable during los = 0: ais insertion on rdpn/rdnn/rclkn is disabled during los = 1: ais insertion on rdpn/rdnn/rclkn is enabled during los atao 0 0 automatically transmit all ones during los (enabled only when patt[1:0] = 00) = 0: disabled = 1: automatically transmit all ones pattern at ttipn/tringn during los. table-49 maint1: maintenance function control register 1 (continued) (r/w, address = x2ch) symbol bit default description table-50 maint2: maintenance function control register 2 (r/w, address = x2dh) symbol bit default description - 7-6 00 reserved. tnlp_l[1:0] 5-4 00 defines the length of the user-programmable transmit inband loopback activate/deactivate code contained in tnlp register. the default selection is 5 bits length. = 00: 5-bit activate code in tnlp [4:0] = 01: 6-bit activate code in tnlp [5:0] = 10: 7-bit activate code in tnlp [6:0] = 11: 8-bit activate code in tnlp [7:0] rnlpa_l[1:0] 3-2 00 defines the length of the user-programmable receive inband loopback activate code contained in rnlpa regis- ter. = 00: 5-bit activate code in rnlpa [4:0] = 01: 6-bit activate code in rnlpa [5:0] = 10: 7-bit activate code in rnlpa [6:0] = 11: 8-bit activate code in rnlpa [7:0] rnlpd_l[1:0] 1-0 01 defines the length of the user-programmabl e receive inband loopback deactivate code contained in rnlpd reg- ister. = 00: 5-bit deactivate code in rnlpd [4:0] = 01: 6-bit deactivate code in rnlpd [5:0] = 10: 7-bit deactivate code in rnlpd [6:0] = 11: 8-bit deactivate code in rnlpd [7:0] table-51 maint3: maintenance function control register 3 (r/w, address = x2eh) symbol bit default description tnlp[7:0] 7-0 (000)00001 defines the user-programmable transmit inband loopback activate/deactivate code. the default selection is 00001. tnlp[7:0] form the 8-bit repeating code tnlp[6:0] form the 7-bit repeating code tnlp[5:0] form the 6-bit repeating code tnlp[4:0] form the 5-bit repeating code
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 51 february 5, 2009 table-52 maint4: maintenance function control register 4 (r/w, address = x2fh) symbol bit default description rnlpa[7:0] 7-0 (000)00001 defines the user-programmable receive inband loopback activate code. the default selection is 00001. rnlpa[7:0] form the 8-bit repeating code rnlpa[6:0] form the 7-bit repeating code rnlpa[5:0] form the 6-bit repeating code rnlpa[4:0] form the 5-bit repeating code table-53 maint5: maintenance function control register 5 (r/w, address =x30h) symbol bit default description rnlpd[7:0] 7-0 (00)001001 defines the user-programmable receive inband loopback deactivate code. the default selection is 001001 . rnlpd[7:0] form the 8-bit repeating code rnlpd[6:0] form the 7-bit repeating code rnlpd[5:0] form the 6-bit repeating code rnlpd[4:0] form the 5-bit repeating code table-54 maint6: maintenance function control register 6 (r/w, address = x31h) symbol bit default description - 7 0 reserved. bpv_ins 6 0 bpv error insertion a ?0? to ?1? transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream. this bit must be cleared and set again for a subsequent error to be inserted. err_ins 5 0 prbs/qrss logic error insertion a ?0? to ?1? transition on this bit will cause a single prbs/qrss logic error to be inserted into the transmit prbs/ qrss data stream. this bit must be cleared and set again for subsequent error to be inserted. exz_def 4 0 exz definition select = 0: ansi = 1: fcc err_sel[1:0] 3-2 00 these bits choose which type of error will be counted = 00: the prbs logic error is counted by a 16-bit error counter. = 01: the exz error is counted by a 16-bit error counter. = 10: the received cv (bpv) error is counted by a 16-bit error counter. = 11: both cv (bpv) and exz errors ar e counted by a 16-bit error counter. cnt_md 1 0 counter operation mode select = 0: manual report mode = 1: auto report mode cnt_stop 0 0 = 0: enable counter. = 1: counter is latched.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 52 february 5, 2009 4.3.6 transmit and receive termination register 4.3.7 interrupt control registers table-55 term: transmit and receive termination configuration register (r/w, address = x32h) symbol bit default description - 7-6 00 reserved t_term[2:0] 5-3 000 these bits select the internal termination for transmit line impedance matching. = 000: internal 75 ? impedance matching = 001: internal 120 ? impedance matching = 010: internal 100 ? impedance matching = 011: internal 110 ? impedance matching =1xx: selects external impedance matching resistors for e1 mode only. t1/j1 does not require external imped- ance resistors (see table-14 ). r_term[2:0] 2-0 000 these bits select the internal termination for receive line impedance matching. = 000: internal 75 ? impedance matching = 001: internal 120 ? impedance matching = 010: internal 100 ? impedance matching = 011: internal 110 ? impedance matching = 1xx: selects external impedance matching resistors (see table-16 ). table-56 intenc0: interrupt mask register 0 (r/w, address = x33h) symbol bit default description - 7 0 reserved. nlpa_ie 6 0 in-band loopback activate code detect interrupt mask = 1: in-band loopback activate code detect interrupt enabled = 0: in-band loopback activate code detect interrupt masked nlpd_ie 5 0 in-band loopback deactivate code detect interrupt mask = 1: in-band loopback deactivate code detect interrupt enabled = 0: in-band loopback deactivate code detect interrupt masked prbs_ie 4 0 prbs synchronic si gnal detect interrupt mask = 1: prbs synchronic signal detect interrupt enabled = 0: prbs synchronic signal detect interrupt masked tclk_ie 3 0 tclk loss detect interrupt mask = 1: tclk loss detect interrupt enabled = 0: tclk loss detect interrupt masked df_ie 2 0 driver failure interrupt mask = 1: driver failure interrupt enabled = 0: driver failure interrupt masked ais_ie 1 0 alarm indication signal interrupt mask = 1: alarm indication signal interrupt enabled = 0: alarm indication signal interrupt masked los_ie 0 0 loss of signal interrupt mask = 1: loss of signal interrupt enabled = 0: loss of signal interrupt masked
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 53 february 5, 2009 table-57 intenc1: interrupt mask register 1 (r/w, address = x34h) symbol bit default description - 7 0 reserved. dac_ie 6 0 dac arithmetic overflow interrupt mask = 1: dac arithmetic overflow interrupt enabled = 0: dac arithmetic overflow interrupt masked tja_ie 5 0 ja in transmit path overflow/underflow interrupt mask = 1: ja overflow interrupt enabled = 0: ja overflow interrupt masked rja_ie 4 0 ja in receive path overflow/underflow interrupt mask = 1: ja underflow interrupt enabled = 0: ja underflow interrupt masked err_ie 3 0 prbs/qrss logic erro r detect interrupt mask = 1: prbs/qrss logic error detect interrupt enabled = 0: prbs/qrss logic error detect interrupt masked exz_ie 2 0 receive excess zeros interrupt mask = 1: receive excess zeros interrupt enabled = 0: receive excess zeros interrupt masked cv_ie 1 0 receive error interrupt mask = 1: receive error interrupt enabled = 0: receive error interrupt masked cnt_ie 0 0 counter overflow interrupt mask = 1: counter overflow interrupt enabled = 0: counter overflow interrupt masked
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 54 february 5, 2009 table-58 intes: interrupt trigger edges select register (r/w, address = x35h) symbol bit default description - 7 0 reserved. nlpa_ies 6 0 this bit determines the inband loopback activate code interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the nlpa_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the nlpa_s bit in the stat0 status register. nlpd_ies 5 0 this bit determines the inband loopback deactivate code interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the nlpd_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the nlpd_s bit in the stat0 status register. prbs_ies 4 0 this bit determines the prbs/qrss synchronization status interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the prbs_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the prbs_s bit in the stat0 status register. tclk_ies 3 0 this bit determines the tclk loss interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the tclk_los bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the tclk_los bit in the stat0 status register. df_ies 2 0 this bit determines the driver failure interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the df_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the df_s bit in the stat0 status register. ais_ies 1 0 this bit determines the ais interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the ais_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the ais_s bit in the stat0 status register. los_ies 0 0 this bit determines the los interrupt event. = 0: interrupt event is defined as a ?0? to ?1? transition of the los_s bit in the stat0 status register = 1: interrupt event is defined as either a ?0? to ?1? transition or a ?1? to ?0? transition of the los_s bit in the stat0 status register.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 55 february 5, 2009 4.3.8 line status registers table-59 stat0: line status register 0 (real time status monitor) (r, address = x36h) symbol bit default description arlp_s 7 0 indicating the auto remote loop back status = 0: the remote loop is inactive. if enabled auto remote loop back by setting bit arlp, the remote loop is switched off automatically upon detection of the in-band loop deactivate code for at least 5.1 s, according to ansi t1. 403 requirements. =1: the remote loop is active (closed). if enabled by bit arlp, the remote loop is switched on automatically upon detection of the in-band loop activate code for at least 5.1 s. nlpa_s 6 0 inband loopback activate code receive status indication = 0: no inband loopback activate code is detected = 1: activate code has been detected for more than t ms. even there is bit error, this bit remains set as long as the bit error rate is less than 10 -2 . note1: if automatic remote loop switching is disabled (arlp = 0), t = 40 ms if automatic remote loop switching is enabled (arlp = 1), t= 5.1s. the rising edge of this bit actives the remote loop operation in local end. note2: if nlpa_ie=1, 0 to 1 transition on this bit causes an activate code detected interrupt if nlpa _ies bit is 0; any change of this bit causes an activate code detected interrupt if nlpa _ies bit is set to 1. nlpd_s 5 0 inband loopback deactivate code receive status indication = 0: no inband loopback deactivate code is detected = 1: the inband loopback deactivate code has been detected for more than t. even there is a bit error, this bit remains set as long as the bit error rate is less than 10 -2 . note 1: if automatic remote loop switching is disabled (arlp = 0), t = 40 ms.if automatic remote loop switching is enabled (arlp = 1), t= 5.1s. the rising edge of this bit disables the remote loop back operation. note2: if nlpd_ie=1, a 0 to 1 transition on this bit causes a deactivate code detected interrupt if nlpd _ies bit is 0 any change of this bit causes a deactivate code detected interrupt if nlpd _ies bit is set to 1. prbs_s 4 0 synchronous status indica tion of prbs/qrss (real time) = 0: 2 15 -1 (e1) prbs or 2 20 -1 (t1/j1) qrss is not detected = 1: 2 15 -1 (e1) prbs or 2 20 -1 (t1/j1) qrss is detected. note: if prbs_ie=1, 0 to 1 transition on this bit causes an synchronous status detected interrupt if prbs _ies bit is 0 any change of this bit causes an interrupt if prbs_ies bit is set to 1. tclk_los 3 0 tclkn loss indication = 0: normal = 1: tclkn pin has not toggled for more than 70 mclk cycles. note: if tclk_los_ie=1, 0 to 1 transition on this bi t causes an interrupt if tclk _ies bit is 0 any change of this bit causes an interrupt if tclk_ies bit is set to 1.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 56 february 5, 2009 df_s 2 0 line driver status indication = 0: normal operation = 1: line driver short circuit is detected. note: if df_ie=1, 0 to 1 transition on this bit causes an interrupt if df _ies bit is 0. any change of this bit causes an interrupt if df_ies bit is set to 1. ais_s 1 0 alarm indication signal status detection = 0: no ais signal is detected in the receive path = 1: ais signal is detected in the receive path note: if ais_ie=1, 0 to 1 transition on this bit causes an interrupt if ais _ies bit is 0. any change of this bit causes an interrupt if ais_ies bit is set to 1. los_s 0 0 loss of signal status detection = 0: loss of signal on rtip/rring is not detected = 1: loss of signal on rtip/rring is detected note: if los_ie=1, 0 to 1 transition on this bit causes an interrupt if los _ies bit is 0 any change of this bit causes an interrupt if los_ies bit is set to 1 table-59 stat0: line status register 0 (real time status monitor) (continued) (r, address = x36h) symbol bit default description
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 57 february 5, 2009 table-60 stat1: line status register 1 (real time status monitor) (r, address = x37h) symbol bit default description - 7-6 00 reserved -50reserved latt[4:0] 4-0 00000 line attenuation indication in db relative to a 3 v peak pulse level 00000 0 to 2 db 00001 2 to 4 db 00010 4 to 6 db 00011 6 to 8 db 00100 8 to 10 db 00101 10 to 12 db 00110 12 to 14 db 00111 14 to 16 db 01000 16 to 18 db 01001 18 to 20 db 01010 20 to 22 db 01011 22 to 24 db 01100 24 to 26 db 01101 26 to 28 db 01110 28 to 30 db 01111 30 to 32 db 10000 32 to 34 db 10001 34 to 36 db 10010 36 to 38 db 10011 38 to 40 db 10100 40 to 42 db 10101 42 to 44 db 10110-11111 >44 db table-61 tjitt: jitter measure value indicate register (transmit path) (r/w, address = x38h) symbol bit default description -70reserved tjitt[6:0] 6-0 000000 when tjitt_test=0, these bits indicates current jitter measure value. when tjitt_test=1, these bits indicates jitter measure p-p value after last read (reset by a read) table-62 tjitt: jitter measure value indicate register (receive path) (r/w, address = x39h) symbol bit default description -70reserved rjitt[6:0] 6-0 000000 when rjitt_test=0, these bits indicates current jitter measure value. when rjitt_test=1, these bits indicates jitter measure p-p value after last read (reset by a read)
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 58 february 5, 2009 4.3.9 interrupt status registers table-63 ints0: interrupt status register 0 (this register is cleared if a ?1? is written to it.) (r/w, address = x3ah) symbol bit default description -70reserved nlpa_is 6 0 this bit indicates the occurrence of the inband loopback activate code interrupt event. = 0: no inband loopback activate code interrupt event occurred = 1: inband loopback activate code interrupt event occurred nlpd_is 5 0 this bit indicates the occurrence of the inband loopback deactivate code interrupt event. = 0: no inband loopback deactivate code interrupt event occurred = 1: interrupt event of the received inband loopback deactivate code occurred. prbs_is 4 0 this bit indicates the occurrence of the interrupt event generated by the prbs/qrss synchronization status. = 0: no prbs/qrss synchronization status interrupt event occurred = 1: prbs/qrss synchronization status interrupt event occurred tclk_los_is 3 0 this bit indicates the occurrence of the interrupt event generated by the tclkn loss detection. = 0: no tclkn loss interrupt event. = 1:tclkn loss interrupt event occurred. df_is 2 0 this bit indicates the occurrence of the interrupt event generated by the driver failure. = 0: there is no status change on the df_s bit (b2, t1/j1-036h,...). = 1: when the df_ies bit (b2, t1/j1-035h,...) is ?0?, the ?1? on this bit indicates there is a transition from ?0? to ?1? on the df_s bit (b2, t1/j1-036h,...); when the df_ies bit (b 2, t1/j1-035h,...) is ?1?, the ?1? on this bit indicates there is a transition from ?0? to ?1? or from ?1? to ?0? on the df_s bit (b2, t1/j1-036h,...). ais_is 1 0 this bit indicates the alarm indication signal interrupt status detection. = 0: no ais happen since last reset ais_is = 1: 0 to 1 transition on bit ais_s if ais_i es=0, or any change on bit ais_s if ais_ies=1 los_is 0 0 this bit indicates the occurrence of the los (loss of signal) interrupt event. = 0: there is no status change on the los_s bit (b0, t1/j1-036h,...). = 1: when the los_ies bit (b0, t1/j1-035h,...) is ?0?, the ?1? on this bit indicates there is a transition from ?0? to ?1? on the los_s bit (b0, t1/j1-036h,...); when the los_ies bit (b0, t1/j1-035h,...) is ?1?, the ?1? on this bit indicates there is a transition from ?0? to ?1? or from ?1? to ?0? on the los_s bit (b0, t1/j1-036h,...).
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter programming information 59 february 5, 2009 4.3.10 counter registers table-64 ints1: interrupt status register 1 (this register is cleared if a ?1? is written to it.) (r/w, address = x3bh) symbol bit default description -70reserved dac_is 6 0 this bit indicates the occurrence of the pulse amplitude overflow of arbitrary waveform generator interrupt event. = 0: no pulse amplitude overflow of arbitrary waveform generator interrupt event occurred = 1: the pulse amplitude overflow of arbitrary waveform generator interrupt event occurred tja_is 5 0 this bit indicates the occurrence of the jitter attenuator overflow interrupt event. = 0: no ja overflow interrupt event occurred = 1: a overflow interrupt event occurred rja_is 4 0 this bit indicates the occurrence of the jitter attenuator underflow interrupt event. = 0: no ja underflow interrupt event occurred = 1: ja underflow interrupt event occurred err_is 3 0 this bit indicates the occurrence of the interrupt event generated by the detected prbs/qrss logic error. = 0: no prbs logic error has been received since last reset err_is = 1: prbs/qrss logic error interrupt event occurred exz_is 2 0 this bit indicates the occurrence of the excessive zeros interrupt event. = 0: no excessive zeros has been received since last reset. exz_is = 1: exz interrupt event occurred cv_is 1 0 this bit indicates the occurrence of the code violation interrupt event. = 0: no code violation is received since last reset cv_is = 1: code violation has received and generate an interrupt request if no masked cntov_is 0 0 this bit indicates the occurrence of the counter overflow interrupt event. = 0: counter is not over since last reset cntov_is = 1: counter is over and generate an interrupt request if no masked table-65 cntl: error counter l-byte register 0 (r, address = x3ch) symbol bit default description cnt_l[7:0] 7-0 00h this register contains the lower eight bits of the 16-bit error counter. cnt_l[0] is the lsb. table-66 cnth: error counter h-byte register 1 (r, address = x3d) symbol bit default description cnt_h[7:0] 7-0 00h this register contains the upper eight bits of the 16-bit error counter. cnt_h[7] is the msb. table-67 refc: e1 reference clock output control (r/w, address = x3e) symbol bit default description - 7-6 000000 reserved refh_los: 0 0 in case of los, this bit determines the outputs on the refa_out and refb_out pins. = 0: output mclk. = 1: output high level.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter ieee std 1149.1 jtag test access port 60 february 5, 2009 5 ieee std 1149.1 jtag test access port the idt82p5088 supports the digital boundary scan specification as described in the ieee 1149.1 standards. the boundary scan architecture consis ts of data and instruction regis- ters plus a test access port (tap) controller. control of the tap is per- formed through signals applied to the test mode select (tms) and test clock (tck) pins. data is shifted into the registers via the test data input (tdi) pin, and shifted out of the registers via the test data output (tdo) pin. both tdi and tdo are clocked at a rate determined by tck. the jtag boundary scan register s include bsr (boundary scan reg- ister), idr (device identification r egister), br (bypass register) and ir (instruction register). these will be described in the following pages. refer to for architecture. figure-23 jtag architecture bsr (boundary scan register) idr (device identification register) br (bypass register) ir (instruction register) mux tdo tdi tck tms trst control<6:0> mux select high impedance enable tap (test access port) controller parallel latched output digital output pins digital input pins
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter ieee std 1149.1 jtag test access port 61 february 5, 2009 5.1 jtag instructions and instruction reg- ister the ir (instruction register) with instruction decode block is used to select the test to be executed or t he data register to be accessed or both. the instructions are shifted in lsb first to this 3-bit register. see table- 68 for details of the codes and the instructions related. 5.2 jtag data register 5.2.1 device identification register (idr) the idr can be set to define the producer number, part number and the device revision, which can be used to verify the proper version or re- vision number that has been used in the system under test. the idr is 32 bits long and is partitioned as in table-69 . data from the idr is shifted out to tdo lsb first. 5.2.2 bypass register (br) the br consists of a single bit. it can provide a serial path between the tdi input and tdo output, bypassing the bsr to reduce test access times. 5.2.3 boundary scan register (bsr) the bsr can apply and read test patterns in parallel to or from all the digital i/o pins. the bsr is a 98 bits long shift register and is initialized and read using the instruction extest or sample/preload. each pin is related to one or more bits in the bsr. for details, please refer to the bsdl file. table-68 instruction register description ir code instruction comments 000 extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between tdi and tdo. the signal on the input pins can be sam- pled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. the signal on the output pins can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. 100 sample / preload the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan re gister is placed between tdi and tdo. the normal path between idt82p5088 lo gic and the i/o pins is maintained. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. 110 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identi fication code can then be shifted out using the shift-dr state. 111 bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is us ed to bypass the device. table-69 device identifica tion register description bit no. comments 0 set to ?1? 1-11 producer number 12-27 part number 28-31 device revision
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter ieee std 1149.1 jtag test access port 62 february 5, 2009 5.2.4 test access port controller the tap controller is a 16-st ate synchronous state machine. figure-24 shows its state diagram following the description of each state. note that the figure contains two main branches to access either the data or instruc- tion registers. the value shown next to each state transition in this figure states the value present at tms at each rising edge of tck. please refer to table-70 for details of the state description. table-70 tap controller state description state description test logic reset in this state, the test logic is disabled. the device is set to normal operation. during initialization, the de vice initializes the instruction register with the idcode instruction. regardless of the original state of the controller, the controller enters the test-logic-reset sta te when the tms input is held high for at least 5 rising edges of tck. the controller remains in this state while tms is high. the device p rocessor auto- matically enters this state at power-up. run-test/idle this is a controller state between scan operations. once in this state, the controller remains in the state as lon g as tms is held low. the instruction register and all test data registers retain their previous state. when tms is high and a rising edge is applied to tck, the control- ler moves to the select-dr state. select-dr-scan this is a temporary controller state and the instruction does not change in this state. the test data register se lected by the current instruc- tion retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the controller move s into the cap- ture-dr state and a scan sequence for the selected test data register is initiated. if tms is held high and a rising edge appli ed to tck, the controller moves to the select-ir-scan state. capture-dr in this state, the boundary scan register captures input pin data if the current inst ruction is extest or sample/prel oad. the instruc- tion does not change in this state. the other test data registers, which do not have parallel input, are not changed. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or the shift-dr s tate if tms is low. shift-dr in this controller state, the test data register connected between tdi and tdo as a result of the current instruction s hifts data on stage toward its serial output on each rising edge of tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or remains in the shift-dr state i f tms is low. exit1-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state. pause-dr the pause state allows the test controller to temporarily halt the shifting of data through the test data register in t he serial path between tdi and tdo. for example, this state could be used to allow the tester to reload its pin memory from disk during application of a l ong test sequence. the test data register selected by the current instruction retains its previous value and the instruction does not ch ange during this state. the controller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-dr state. exit2-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state. update-dr the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in resp onse to the extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is l atched into the parallel output of this register from the shift-register path on the falling edge of tck. the data held at the latched parallel output changes only in this state. all shift-register stages in the test data register selected by the current instruction retain thei r previous value and the instruction does not change during this state. select-ir-scan this is a temporary controller state. the test data register selected by the current instruction retains its prev ious state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves into the capture-ir state, and a scan sequence for the instruc- tion register is initiated. if tms is held high and a rising edge is applied to tck, the controller moves to the test-logic-res et state. the instruction does not change during this state. capture-ir in this controller state, the shift register contained in the instruction register loads a fixed value of '100' on th e rising edge of tck. this sup- ports fault-isolation of the board-level serial test data path. data registers selected by the current instruction retain their value and the instruction does not change during this state. when the controller is in this state and a rising edge is applied to tck, the co ntroller enters the exit1-ir state if tms is held high, or the shift-ir state if tms is held low. shift-ir in this state, the shift register contained in the instruction register is connected between tdi and tdo and shifts dat a one stage towards its serial output on each rising edge of tck. the test data register selected by the current instruction retains its previous value and the instruc- tion does not change during this state. when the controller is in this state and a rising edge is applied to tck, the controlle r enters the exit1- ir state if tms is held high, or remains in the shift-ir state if tms is held low.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter ieee std 1149.1 jtag test access port 63 february 5, 2009 figure-24 jtag state diagram exit1-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state. pause-ir the pause state allows the test controller to temporarily halt the shifting of data through the instruction register. t he test data register selected by the current instruction retains its previous value and the instruction does not change during this state. the contr oller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-ir state. exit2-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. update-ir the instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction retain their previous value. table-70 tap controller state description (continued) state description test-logic reset run test/idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 0 1 1 1 00 00 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 64 february 5, 2009 6 test specifications 6.1 absolute maximum ratings caution: long-term exposure to absolute maximum ratings may affect the device?s reliability, and permanent damage may occur if the rating is exceeded during operation. functional operation under these conditions is not implied. the device should be operated under recom- mended operating conditions. 6.2 recommended op erating conditions min max storage temperature -65 c +150 c voltage on vddar/vddat/vddax/vddab/vddap w.r.t. gnd -0.5 v 4.6 v voltage on vdddio w.r.t. gnd -0.5 v 4.6 v voltage on vdddc w.r.t. gnd -0.5 v 2.2 v voltage on any input digital pin -0.5 v 6 v voltage on any input analog pin -0.5 v vddar/vddat/vddax/ vddab/vddap + 0.5 esd performance (hbm) 2000 v latch-up current on any pin 1.5 x inormal * maximum junction temperature 150 maximum allowed power dissipation (package) 2.57w note: * inormal is the total current in normal operation mode. parameter description min. typ. max unit top operating temperature range -40 25 85 c vdddio digital io power supply 3.0 3.3 3.6 v vddar/vddat/vddax/vddab/vddap ana log io power supply 3.13 3.3 3.47 v vdddc digital core power 1.68 1.8 1.98 v vil input low voltage 0 0.8 v vih input high voltage 2.0 3.3 v
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 65 february 5, 2009 6.3 d.c. characteristics @ ta = -40 to +85 c, vdddio = 3.3 v + 0.3 v, vdddc = 1.8 + 10% paramete r description min. typ. max unit test conditions vol output low voltage 0.40 v vdddio = min, iol = 4 ma, 8 ma voh output high voltage 2.4 v vdddio = min, ioh = 4 ma, 8 ma vt+ schmitt trigger input low to high threshold point for ios with schmitt trigger 1.35 v vt- schmitt trigger input high to low threshold point for ios with schmitt trigger 1.02 v r pu pullup resistor in pull-up ios 50 70 115 k ? iil input low current -1 0 +1 a vil = gndd iih input high current -1 0 +1 a vih = vdddio iol d output low current 8 ma vo = vol, d7 - d0 ioh d output high current 8 ma vo = voh, d7 - d0 iol output low current 4 ma vo = vol, except d7 - d0 ioh output high current 4 ma vo = voh, except d7 - d0 c in input digital pin capacitance 10 pf i zl leakage current of digital output in high-impedance mode -10 10 a gnd < vo < vdddio p power dissipation 800 mw with the prbs pattern, excluding loading dissipation p33 power dissipation in 3.3 v domain 650 mw p18 power dissipation in 1.8 v domain 150 mw
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 66 february 5, 2009 6.4 t1/j1 line receiver el ectrical characteristics parameter min. typ. max unit test conditions receiver sensitivity short haul with cable loss @ 772 khz: long haul with cable loss @ 772 khz: 10 36 db with nominal pulse amplitude of 3.0 v for 100 ? termina- tion analog los level short haul: long haul: 4 800 48 mvp-p db a los level is programmable for long haul. allowable consecutive zeros before los t1.231 - 1993: i.431: 175 1544 los reset 12.5 % ?one?s g.775, etsi 300233 receive intrinsic jitter 10 hz - 8 khz 10 hz - 40 khz 8 khz - 40 khz wide band 0.02 0.025 0.025 0.05 u.i. u.i. u.i. u.i. ja is enabled input jitter tolerance 0.1 hz - 1 hz: 4.9 hz - 300 hz: 10 khz - 100 khz: 138.0 28.0 0.4 u.i. u.i. u.i. at&t62411 receiver differential input impedance 20 k ? input termination resistor tolerance 1% receive return loss 39 khz - 77 khz: 77 khz - 1.544 mhz: 1.544 mhz - 2.316 mhz 20 20 20 db db db g.703 internal termination
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 67 february 5, 2009 6.5 e1 line receiver elec trical characteristics 6.6 t1/j1 line transmitter el ectrical characteristics parameter min. typ. max unit test conditions receiver sensitivity short haul with cable loss @ 1024 khz: long haul with cable loss @ 1024 khz: 10 43 db with nominal pulse amplitude of 3.0 v for 120 ? and 2.37 v for 75 ? termination analog los level short haul: long haul: 4 800 48 mvp-p db a los level is programmable for long haul. allowable consecutive zeros before los g.775: i.431 / etsi300233: 32 2048 los reset 12.5 % ?one?s g.775, etsi 300233 receive intrinsic jitter 0.05 u.i. ja is enabled; wide band input jitter tolerance 1 hz - 20 hz: 20 hz - 2.4 khz: 18 khz - 100 khz: 37 5 2 u.i. u.i. u.i. g.823, with 6 db cable attenuation receiver differential input impedance 20 k ? input termination resistor tolerance 1% receive return loss 51 khz - 102 khz: 102 khz - 2.048 mhz: 2.048 mhz - 3.072 mhz 20 20 20 db db db g.703 internal termination parameter min. typ. max unit output pulse amplitudes 2.4 3.0 3.6 v zero (space) level -0.15 0.15 v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses (t1.102) 200 mv output pulse width at 50% of nominal amplitude 338 350 362 ns pulse width variation at the half amplitude (t1.102) 20 ns imbalance between positive and negative pulses amplitude (t1.102) 0.95 1.05
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 68 february 5, 2009 6.7 e1 line transmitter electrical characteristics transmit return loss 39 khz - 77 khz: 77 khz - 1.544 mhz: 1.544 mhz - 2.316 mhz: 20 15 12 db db db intrinsic transmit jitter (tsck is jitter free) 10 hz - 8 khz: 8 khz - 40 khz: 10 hz - 40 khz: wide band: 0.020 0.025 0.025 0.050 u.i.p-p u.i.p-p u.i.p-p u.i.p-p line short circuit current 110 ma ip-p parameter min. typ. max unit parameter min. typ. max unit output pulse amplitudes e1, 75 ? load: e1, 120 ? load: 2.14 2.7 2.37 3.0 2.60 3.3 v v zero (space) level e1, 75 ? load: e1, 120 ? load: -0.237 -0.3 0.237 0.3 v v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses (t1.102) 200 mv output pulse width at 50% of nominal amplitude 232 244 256 ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 ratio of the width of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 transmit return loss (g.703) e1, 75 ? / 120 ? 51 khz - 102 khz: 102 khz - 2.048 mhz: 2.048 mhz - 3.072 mhz: 20 15 12 db db db intrinsic transmit jitter (tsck is jitter free) 20 hz - 100 khz 0.050 u.i. line short circuit current 110 ma ip-p
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 69 february 5, 2009 6.8 transmitter and receiver timing characteristics 1.relative to nominal frequency, mclk= 32 ppm 2.rclk duty cycle widths will vary depending on extent of received pulse jitter displacement. maximum and minimum rclk duty cyc les are for worst case jitter conditions (0.2ui displacement for e1 per itu g.823). 3.for all digital outputs. c load = 15pf symbol parameter min typ max unit osci frequency e1: t1/j1: 2.048 x n (n = 1, 2, 3, 4) 1.544 x n (n = 1, 2, 3, 4) mhz mclk tolerance -32 32 ppm mclk duty cycle 30 70 % transmit path tclk frequency e1: t1/j1: 2.048 1.544 mhz tclk tolerance -50 +50 ppm tclk duty cycle 10 90 % t1 transmit data setup time 40 ns t2 transmit data hold time 40 ns delay time of thz low to driver high impedance 10 us delay time of tclk low to driver high impedance 75 u.i. receive path clock recovery capture range 1 e1 80 ppm t1/j1 180 rclk duty cycle 2 40 50 60 % t4 rclk pulse width 2 e1: t1/j1: 457 607 488 648 519 689 ns t5 rclk pulse width low time e1: t1/j1: 203 259 244 324 285 389 ns t6 rclk pulse width high time e1: t1/j1: 203 259 244 324 285 389 ns rise/fall time 3 20 ns t7 receive data setup time e1: t1/j1: 200 200 244 324 ns t8 receive data hold time e1: t1/j1: 200 200 244 324 ns
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 70 february 5, 2009 figure-25 transmit system interface timing figure-26 receive system interface timing 6.9 jitter tolerance 6.9.1 t1/j1 mode tdnn tdn/tdpn tclkn t1 t2 rdnn/cvn rdpn/rdn rclkn t4 t7 t6 t7 t5 t8 t8 (rclk_sel = 1) (rclk_sel = 0) rdpn/rdn rdnn/cvn jitter tolerance min. typ. max unit standard 1 hz 138.0 u.i. at&t 62411 4.9 hz - 300 hz 28.0 u.i. 10 khz - 100 khz 0.4 u.i.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 71 february 5, 2009 figure-27 t1/j1 jitter tolerance performance requirement 6.9.2 e1 mode jitter tolerance min. typ. max unit standard 1 hz 37 u.i. g.823 cable attenuation is 6 db 20 hz - 2.4 khz 1.5 u.i. 18 khz - 100 khz 0.2 u.i.
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 72 february 5, 2009 figure-28 e1 jitter tolerance performance requirement
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 73 february 5, 2009 6.10 jitter transfer 6.10.1 t1/j1 mode t1/j1 jitter transfer performance is required by at&t pub.62411. parameter min. typ. max unit jitter attenuator latency delay 32-bit fifo: 64-bit fifo: 128-bit fifo: 16 32 64 u.i. u.i. u.i. input jitter tolerance before fifo overflow or underflow 32-bit fifo: 64-bit fifo: 128-bit fifo: 28 58 120 u.i. u.i. u.i. parameter min. typ. max unit @ 1 hz 0 db @ 20 hz 0 @ 1 khz +33.3 @ 1.4 khz 40 @ 70 khz 40
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 74 february 5, 2009 figure-29 t1/j1 jitter transfer performance requirement (at&t62411 / gr-253-core / tr-tsy-000009) 6.10.2 e1 mode e1 jitter transfer perform ance is required by g.736. parameter min. typ. max unit @ 3 hz -0.5 db @ 40 hz -0.5 @ 400 hz +19.5 @ 100 khz +19.5
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 75 february 5, 2009 figure-30 e1 jitter transfer performance requirement (g.736) table-71 jtag timing characteristics symbol parameter min typ max unit t1 tck period 100 ns t2 tms to tck setup time tdi to tck setup time 25 ns t3 tck to tms hold time tck to tdi hold time 25 ns t4 tck to tdo delay time 50 ns
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter test specifications 76 february 5, 2009 figure-31 jtag interface timing tck t1 t2 t3 tdo tms tdi t4
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter microcontroller interface timing characteristics77 february 5, 2009 7 microcontroller interface timing characteristics 7.1 motorola non-multiplexed mode 7.1.1 read cycle specification figure-32 motorola non-multiplexed mode read cycle 7.1.2 write cycle specification symbol parameter min max units trc read cycle time 237 ns tdw valid ds width 232 ns trwv delay from ds to valid read signal 21 ns trwh r w to ds hold time 134 ns tav delay from ds to valid address 21 ns tadh address to ds hold time 134 ns tprd ds to valid read data propagation delay 206 ns tdaz delay from read data active to high z 5 20 ns trecovery recovery time from read cycle 5 ns a[x:0] valid address ds + cs r w read d[7:0] trwv valid data tdaz tadh trwh tprd trc tdw tav trecovery symbol parameter min max units twc write cycle time 237 ns tdw valid ds width 232 ns trwv delay from ds to valid write signal 21 ns trwh r w to ds hold time 165 ns tav delay from ds to valid address 21 ns
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter microcontroller interface timing characteristics78 february 5, 2009 figure-33 motorola non-mu ltiplexed mode write cycle 7.2 intel non-multiplexed mode 7.2.1 read cycle specification tah address to ds hold time 165 ns tdv delay from ds to valid write data 83 ns tdhw write data to ds hold time 165 ns trecovery recovery time from write cycle 5 ns symbol parameter min max units a[x:0] valid address ds + cs r w write d[7:0] tr wv tdhw tah trwh twc tdw tav valid data tdv trecovery symbol parameter min max units trc read cycle time 237 ns trdw valid rd width 232 ns tav delay from rd to valid address 21 ns tah address to rd hold time 134 ns tprd rd to valid read data propagation delay 206 ns tdaz delay from read data active to high z 5 20 ns trecovery recovery time from read cycle 5 ns
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter microcontroller interface timing characteristics79 february 5, 2009 figure-34 intel non-mult iplexed mode read cycle 7.2.2 write cycle specification figure-35 intel non-multiplexed mode write cycle a[x:0] valid address cs + rd read d[7:0] valid data tdaz tah tpr d trdw tav note: the wr pin should be tied to high. trecovery trc symbol parameter min max units twc write cycle time 237 ns twrw valid wr width 232 ns tav delay from wr to valid address 21 ns tah address to wr hold time 165 ns tdv delay from wr to valid write data 83 ns tdhw write data to wr hold time 165 ns trecovery recovery time from write cycle 5 ns a[x:0] valid address wr + cs write d[7:0] tdhw tah twc twrw tav valid data tdv note: the rd pin should be tied to high. trecovery
idt82p5088 universal octal t1/e1/j1 liu with integrated clock adapter microcontroller interface timing characteristics80 february 5, 2009 7.3 spi mode the maximum spi data transfer clock is 2 mhz. figure-36 spi timing diagram symbol description min. max units f op sclk frequency 2.0 mhz t csh min. cs high time 100 ns t css cs setup time 50 ns t csd cs hold time 100 ns t cld clock disable time 50 ns t clh clock high time 205 ns t cll clock low time 205 ns t dis data setup time 50 ns t dih data hold time 150 ns t pd output delay 150 ns t df output disable time 50 ns cs sclk sdi sdo t csh t css high impedance high impedance t csd t clh t cll t dis t dih t pd t df valid input valid output t cld
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